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bench/targets: Minor CRG cleanups.

This commit is contained in:
Florent Kermarrec 2021-06-29 12:36:02 +02:00
parent d16aaa7456
commit e90aa5a4d5
5 changed files with 21 additions and 19 deletions
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8
bench/arty.py
View File

@ -38,6 +38,7 @@ class _CRG(Module, AutoCSR):
# # #
# Main PLL.
self.submodules.main_pll = main_pll = S7PLL(speedgrade=-1)
self.comb += main_pll.reset.eq(~platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk100"), 100e6)
@ -50,6 +51,8 @@ class _CRG(Module, AutoCSR):
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
# DRAM PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~main_pll.locked | self.rst)
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
@ -57,10 +60,9 @@ class _CRG(Module, AutoCSR):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
sys_clk_counter = Signal(32)
self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
# Sys Clk Counter.
self.sys_clk_counter = CSRStatus(32)
self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
self.sync += self.sys_clk_counter.status.eq(self.sys_clk_counter.status + 1)
# Bench SoC ----------------------------------------------------------------------------------------

7
bench/genesys2.py
View File

@ -36,6 +36,7 @@ class _CRG(Module, AutoCSR):
# # #
# Main PLL.
self.submodules.main_pll = main_pll = S7PLL(speedgrade=-2)
self.comb += main_pll.reset.eq(~platform.request("cpu_reset_n"))
main_pll.register_clkin(platform.request("clk200"), 200e6)
@ -45,16 +46,16 @@ class _CRG(Module, AutoCSR):
main_pll.expose_drp()
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# DRAM PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-2)
self.comb += pll.reset.eq(~main_pll.locked | self.rst)
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
sys_clk_counter = Signal(32)
self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
# Sys Clk Counter.
self.sys_clk_counter = CSRStatus(32)
self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
self.sync += self.sys_clk_counter.status.eq(self.sys_clk_counter.status + 1)
# Bench SoC ----------------------------------------------------------------------------------------

7
bench/kc705.py
View File

@ -36,6 +36,7 @@ class _CRG(Module, AutoCSR):
# # #
# Main PLL.
self.submodules.main_pll = main_pll = S7PLL(speedgrade=-2)
self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk200"), 200e6)
@ -45,16 +46,16 @@ class _CRG(Module, AutoCSR):
main_pll.expose_drp()
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# DRAM PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-2)
self.comb += pll.reset.eq(~main_pll.locked | self.rst)
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
sys_clk_counter = Signal(32)
self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
# Sys Clk Counter.
self.sys_clk_counter = CSRStatus(32)
self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
self.sync += self.sys_clk_counter.status.eq(self.sys_clk_counter.status + 1)
# Bench SoC ----------------------------------------------------------------------------------------

9
bench/kcu105.py
View File

@ -39,6 +39,7 @@ class _CRG(Module, AutoCSR):
# # #
# Main PLL.
self.submodules.main_pll = main_pll = USMMCM(speedgrade=-2)
self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk125"), 125e6)
@ -48,11 +49,11 @@ class _CRG(Module, AutoCSR):
main_pll.create_clkout(self.cd_eth, 200e6)
main_pll.expose_drp()
# DRAM PLL.
self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(~main_pll.locked | self.rst)
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
self.specials += [
Instance("BUFGCE_DIV",
p_BUFGCE_DIVIDE = 4,
@ -66,13 +67,11 @@ class _CRG(Module, AutoCSR):
o_O = self.cd_sys4x.clk,
),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
sys_clk_counter = Signal(32)
self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
# Sys Clk Counter.
self.sys_clk_counter = CSRStatus(32)
self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
self.sync += self.sys_clk_counter.status.eq(self.sys_clk_counter.status + 1)
# Bench SoC ----------------------------------------------------------------------------------------

9
bench/xcu1525.py
View File

@ -37,6 +37,7 @@ class _CRG(Module, AutoCSR):
# # #
# Main PLL.
self.submodules.main_pll = main_pll = USPMMCM(speedgrade=-2)
main_pll.register_clkin(platform.request("clk300", channel), 300e6)
main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
@ -44,11 +45,11 @@ class _CRG(Module, AutoCSR):
main_pll.create_clkout(self.cd_uart, 100e6)
main_pll.expose_drp()
# DRAM PLL.
self.submodules.pll = pll = USPMMCM(speedgrade=-2)
self.comb += pll.reset.eq(~main_pll.locked | self.rst)
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
self.specials += [
Instance("BUFGCE_DIV",
p_BUFGCE_DIVIDE = 4,
@ -62,13 +63,11 @@ class _CRG(Module, AutoCSR):
o_O = self.cd_sys4x.clk,
),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
sys_clk_counter = Signal(32)
self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
# Sys Clk Counter.
self.sys_clk_counter = CSRStatus(32)
self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
self.sync += self.sys_clk_counter.status.eq(self.sys_clk_counter.status + 1)
# Bench SoC ----------------------------------------------------------------------------------------