diff --git a/litedram/init.py b/litedram/init.py
index 2620790..3f1ed1d 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -448,7 +448,23 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
 
 def get_sdram_phy_c_header(phy_settings, timing_settings):
     r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
-    r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
+    r += "#include <hw/common.h>\n"
+    r += "#include <generated/csr.h>\n"
+    r += "\n"
+
+    r += "#define DFII_CONTROL_SEL        0x01\n"
+    r += "#define DFII_CONTROL_CKE        0x02\n"
+    r += "#define DFII_CONTROL_ODT        0x04\n"
+    r += "#define DFII_CONTROL_RESET_N    0x08\n"
+    r += "\n"
+
+    r += "#define DFII_COMMAND_CS         0x01\n"
+    r += "#define DFII_COMMAND_WE         0x02\n"
+    r += "#define DFII_COMMAND_CAS        0x04\n"
+    r += "#define DFII_COMMAND_RAS        0x08\n"
+    r += "#define DFII_COMMAND_WRDATA     0x10\n"
+    r += "#define DFII_COMMAND_RDDATA     0x20\n"
+    r += "\n"
 
     phytype = phy_settings.phytype.upper()
     nphases = phy_settings.nphases
diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index db77540..e8f2f06 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -2,7 +2,18 @@
 #define __GENERATED_SDRAM_PHY_H
 #include <hw/common.h>
 #include <generated/csr.h>
-#include <hw/flags.h>
+
+#define DFII_CONTROL_SEL        0x01
+#define DFII_CONTROL_CKE        0x02
+#define DFII_CONTROL_ODT        0x04
+#define DFII_CONTROL_RESET_N    0x08
+
+#define DFII_COMMAND_CS         0x01
+#define DFII_COMMAND_WE         0x02
+#define DFII_COMMAND_CAS        0x04
+#define DFII_COMMAND_RAS        0x08
+#define DFII_COMMAND_WRDATA     0x10
+#define DFII_COMMAND_RDDATA     0x20
 
 #define SDRAM_PHY_K7DDRPHY
 #define SDRAM_PHY_PHASES 4
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index ccb9748..ba42f19 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -2,7 +2,18 @@
 #define __GENERATED_SDRAM_PHY_H
 #include <hw/common.h>
 #include <generated/csr.h>
-#include <hw/flags.h>
+
+#define DFII_CONTROL_SEL        0x01
+#define DFII_CONTROL_CKE        0x02
+#define DFII_CONTROL_ODT        0x04
+#define DFII_CONTROL_RESET_N    0x08
+
+#define DFII_COMMAND_CS         0x01
+#define DFII_COMMAND_WE         0x02
+#define DFII_COMMAND_CAS        0x04
+#define DFII_COMMAND_RAS        0x08
+#define DFII_COMMAND_WRDATA     0x10
+#define DFII_COMMAND_RDDATA     0x20
 
 #define SDRAM_PHY_USDDRPHY
 #define SDRAM_PHY_PHASES 4
diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h
index 1e6ea49..81f975a 100644
--- a/test/reference/sdr_init.h
+++ b/test/reference/sdr_init.h
@@ -2,7 +2,18 @@
 #define __GENERATED_SDRAM_PHY_H
 #include <hw/common.h>
 #include <generated/csr.h>
-#include <hw/flags.h>
+
+#define DFII_CONTROL_SEL        0x01
+#define DFII_CONTROL_CKE        0x02
+#define DFII_CONTROL_ODT        0x04
+#define DFII_CONTROL_RESET_N    0x08
+
+#define DFII_COMMAND_CS         0x01
+#define DFII_COMMAND_WE         0x02
+#define DFII_COMMAND_CAS        0x04
+#define DFII_COMMAND_RAS        0x08
+#define DFII_COMMAND_WRDATA     0x10
+#define DFII_COMMAND_RDDATA     0x20
 
 #define SDRAM_PHY_GENSDRPHY
 #define SDRAM_PHY_PHASES 1