From c30910a9d29954e14494aaf6560424e87a1ba89e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 18 May 2020 23:06:33 +0200 Subject: [PATCH 1/2] init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS. --- litedram/init.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/litedram/init.py b/litedram/init.py index 2620790..6f5c034 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -448,7 +448,20 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings): def get_sdram_phy_c_header(phy_settings, timing_settings): r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n" - r += "#include \n#include \n#include \n\n" + r += "#include \n" + r += "#include \n" + + r += "#define DFII_CONTROL_SEL 0x01\n" + r += "#define DFII_CONTROL_CKE 0x02\n" + r += "#define DFII_CONTROL_ODT 0x04\n" + r += "#define DFII_CONTROL_RESET_N 0x08\n" + + r += "#define DFII_COMMAND_CS 0x01\n" + r += "#define DFII_COMMAND_WE 0x02\n" + r += "#define DFII_COMMAND_CAS 0x04\n" + r += "#define DFII_COMMAND_RAS 0x08\n" + r += "#define DFII_COMMAND_WRDATA 0x10\n" + r += "#define DFII_COMMAND_RDDATA 0x20\n" phytype = phy_settings.phytype.upper() nphases = phy_settings.nphases From fe48a9290c73d843c8a638d2d52f63a4e68823a7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 19 May 2020 08:16:11 +0200 Subject: [PATCH 2/2] test/reference: update. --- litedram/init.py | 3 +++ test/reference/ddr3_init.h | 13 ++++++++++++- test/reference/ddr4_init.h | 13 ++++++++++++- test/reference/sdr_init.h | 13 ++++++++++++- 4 files changed, 39 insertions(+), 3 deletions(-) diff --git a/litedram/init.py b/litedram/init.py index 6f5c034..3f1ed1d 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -450,11 +450,13 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n" r += "#include \n" r += "#include \n" + r += "\n" r += "#define DFII_CONTROL_SEL 0x01\n" r += "#define DFII_CONTROL_CKE 0x02\n" r += "#define DFII_CONTROL_ODT 0x04\n" r += "#define DFII_CONTROL_RESET_N 0x08\n" + r += "\n" r += "#define DFII_COMMAND_CS 0x01\n" r += "#define DFII_COMMAND_WE 0x02\n" @@ -462,6 +464,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): r += "#define DFII_COMMAND_RAS 0x08\n" r += "#define DFII_COMMAND_WRDATA 0x10\n" r += "#define DFII_COMMAND_RDDATA 0x20\n" + r += "\n" phytype = phy_settings.phytype.upper() nphases = phy_settings.nphases diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h index db77540..e8f2f06 100644 --- a/test/reference/ddr3_init.h +++ b/test/reference/ddr3_init.h @@ -2,7 +2,18 @@ #define __GENERATED_SDRAM_PHY_H #include #include -#include + +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 + +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 #define SDRAM_PHY_K7DDRPHY #define SDRAM_PHY_PHASES 4 diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h index ccb9748..ba42f19 100644 --- a/test/reference/ddr4_init.h +++ b/test/reference/ddr4_init.h @@ -2,7 +2,18 @@ #define __GENERATED_SDRAM_PHY_H #include #include -#include + +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 + +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 #define SDRAM_PHY_USDDRPHY #define SDRAM_PHY_PHASES 4 diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h index 1e6ea49..81f975a 100644 --- a/test/reference/sdr_init.h +++ b/test/reference/sdr_init.h @@ -2,7 +2,18 @@ #define __GENERATED_SDRAM_PHY_H #include #include -#include + +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 + +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 #define SDRAM_PHY_GENSDRPHY #define SDRAM_PHY_PHASES 1