From eb6e7a1514d45983f0ee2d89911a01675e45fe5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Wed, 2 Jun 2021 12:28:54 +0200 Subject: [PATCH] test/lpddr4: move dfi_data_to_dq to common code --- test/phy_common.py | 16 +++++++++++++++- test/test_lpddr4.py | 15 ++------------- 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/test/phy_common.py b/test/phy_common.py index 13bfed8..913cd5c 100644 --- a/test/phy_common.py +++ b/test/phy_common.py @@ -15,7 +15,7 @@ from migen import * from litex.gen.sim.core import run_simulation as _run_simulation from litedram.phy import dfi -from litedram.phy.utils import chunks +from litedram.phy.utils import bit, chunks BOLD = '\033[1m' HIGHLIGHT = '\033[91m' @@ -51,6 +51,20 @@ def run_simulation(dut, generators, clocks, debug_clocks=False, **kwargs): _run_simulation(dut, generators, clocks, **kwargs) +def dfi_data_to_dq(dq_i, dfi_phases, dfi_name, nphases, databits, burst): + # e.g. for nphases=8 DDR (burst=16), data on DQ should go in a pattern: + # dq0: p0.wrdata[0], p0.wrdata[16], p1.wrdata[0], p1.wrdata[16], ... + # dq1: p0.wrdata[1], p0.wrdata[17], p1.wrdata[1], p1.wrdata[17], ... + assert burst % nphases == 0 + for p in range(nphases): + data = dfi_phases[p][dfi_name] + for i in range(burst//nphases): + yield bit(i*databits + dq_i, data) + +def dq_pattern(i, dfi_data, dfi_name, **kwargs): + return ''.join(str(v) for v in dfi_data_to_dq(i, dfi_data, dfi_name, **kwargs)) + + class PadsHistory(defaultdict): """Storage for hisotry of per-pad values with human-readable printing diff --git a/test/test_lpddr4.py b/test/test_lpddr4.py index ba8a6b4..81f8a9a 100644 --- a/test/test_lpddr4.py +++ b/test/test_lpddr4.py @@ -13,7 +13,6 @@ from collections import defaultdict from migen import * -from litedram.phy.utils import bit from litedram.phy.lpddr4.simphy import LPDDR4SimPHY, DoubleRateLPDDR4SimPHY from litedram.phy.lpddr4 import simsoc @@ -49,18 +48,8 @@ run_simulation = partial(test.phy_common.run_simulation, clocks={ "sys8x_90_ddr": ( 4, 3), }) - -def dfi_data_to_dq(dq_i, dfi_phases, dfi_name, nphases=8): - # data on DQ should go in a pattern: - # dq0: p0.wrdata[0], p0.wrdata[16], p1.wrdata[0], p1.wrdata[16], ... - # dq1: p0.wrdata[1], p0.wrdata[17], p1.wrdata[1], p1.wrdata[17], ... - for p in range(nphases): - data = dfi_phases[p][dfi_name] - yield bit(0 + dq_i, data) - yield bit(16 + dq_i, data) - -def dq_pattern(i, dfi_data, dfi_name): - return ''.join(str(v) for v in dfi_data_to_dq(i, dfi_data, dfi_name)) +dfi_data_to_dq = partial(test.phy_common.dfi_data_to_dq, databits=16, nphases=8, burst=16) +dq_pattern = partial(test.phy_common.dq_pattern, databits=16, nphases=8, burst=16) class LPDDR4Tests(unittest.TestCase):