From ebba39d928d57b5ac0e619a708e3180630f7112b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 3 Sep 2018 14:17:03 +0200
Subject: [PATCH] README: update

---
 README | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/README b/README
index 436ff5b..dbd1078 100644
--- a/README
+++ b/README
@@ -26,8 +26,7 @@ design flow by generating the verilog rtl that you will use as a standard core.
 PHY:
   - Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
   - Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
-  - Kintex7 DDR3 PHY (1:4 frequency ratio)
-  - Artix7 DDR3 PHY (1:4 frequency ratio)
+  - Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
 Core:
   - Fully pipelined, high performance.
   - Configurable commands depth on bankmachines.