From eca7fc2ddc5c8a45f865297c09bbf64dec66e721 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Apr 2020 08:51:26 +0200 Subject: [PATCH] phy/ecp5ddrphy: remove Bitslip from comment (no longer present). --- litedram/phy/ecp5ddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py index 523105a..c85b0ef 100644 --- a/litedram/phy/ecp5ddrphy.py +++ b/litedram/phy/ecp5ddrphy.py @@ -454,7 +454,7 @@ class ECP5DDRPHY(Module, AutoCSR): # the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2) # # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI - # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA and Bitslip latencies. + # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies. rddata_en_last = Signal.like(rddata_en) self.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last)) self.sync += rddata_en_last.eq(rddata_en)