From ed6c7759b548402483343d1143278be210147091 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Mon, 6 Sep 2021 15:31:30 +0200 Subject: [PATCH] phy/lpddr5/sim: fix double reset with check_timings=False at high frequency --- litedram/phy/lpddr5/sim.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litedram/phy/lpddr5/sim.py b/litedram/phy/lpddr5/sim.py index d0b38ae..a740a40 100644 --- a/litedram/phy/lpddr5/sim.py +++ b/litedram/phy/lpddr5/sim.py @@ -321,7 +321,8 @@ class CommandsSim(Module, AutoCSR): self.submodules.tinit4 = PulseTiming(5) # (min) stabilized CK before CS high; not really applicable in this simulation self.submodules.tinit5 = PulseTiming(ck(2*us)) # (min) idle time before first MRW/MRR cmmand self.submodules.tzqlat = PulseTiming(max(4, ck(30*ns))) # (min) ZQCAL latch quiet time - self.submodules.tpw_reset = PulseTiming(ck(100*ns)) # (min) RESET_n low time for Reset initialization with stable power + tpw_reset_ck = ck(100*ns) if check_timings else 4 # Avoids double reset during initialization at high frequecies + self.submodules.tpw_reset = PulseTiming(tpw_reset_ck) # (min) RESET_n low time for Reset initialization with stable power def with_progress(timing, string, *args, as_clocks=False): current, full = timing.progress()