From ed7eef12d4f428cfb64e44ad1d393f03d9e836c9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 29 Aug 2018 14:15:12 +0200 Subject: [PATCH] phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) --- litedram/phy/s7ddrphy.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index fbabb67..692e2fa 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -433,11 +433,12 @@ class S7DDRPHY(Module, AutoCSR): ] # dqs preamble/postamble + dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency self.comb += [ - dqs_preamble.eq(last_wrdata_en[cwl_sys_latency-1] & - ~last_wrdata_en[cwl_sys_latency]), - dqs_postamble.eq(last_wrdata_en[cwl_sys_latency+1] & - ~last_wrdata_en[cwl_sys_latency]), + dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] & + ~last_wrdata_en[dqs_sys_latency]), + dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+1] & + ~last_wrdata_en[dqs_sys_latency]), ]