From efad6b3ca523acf99bb75f2307886adb1b988f36 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:54:11 +1000 Subject: [PATCH] gen: Add option to specify CSR base for standalone cores Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litedram/gen.py b/litedram/gen.py index dab7bcd..8a28413 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -309,11 +309,13 @@ class LiteDRAMCore(SoCCore): kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False + csr_base = core_config.get("csr_base", 0) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, - cpu_type = cpu_type, - cpu_variant = cpu_variant, + cpu_type = cpu_type, + cpu_variant = cpu_variant, + csr_base = csr_base, **kwargs) # CRG --------------------------------------------------------------------------------------