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bench/arty: add missing eth clock.

This commit is contained in:
Florent Kermarrec 2020-12-10 13:43:31 +01:00
parent 75f87538a5
commit efb1975d00
1 changed files with 4 additions and 0 deletions
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4
bench/arty.py
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@ -34,6 +34,7 @@ class _CRG(Module, AutoCSR):
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_uart = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
@ -43,9 +44,12 @@ class _CRG(Module, AutoCSR):
main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
main_pll.create_clkout(self.cd_clk200, 200e6)
main_pll.create_clkout(self.cd_uart, 100e6)
main_pll.create_clkout(self.cd_eth, 25e6)
main_pll.expose_drp()
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~main_pll.locked)
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)