From c91cbb597d276c33d92808e5a980ad785653ef66 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:53:28 +1000 Subject: [PATCH 1/5] gen: Remove obsolete bus_expose config option Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 1 - 1 file changed, 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 3f5cab1..dab7bcd 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -303,7 +303,6 @@ class LiteDRAMCore(SoCCore): sys_clk_freq = core_config["sys_clk_freq"] cpu_type = core_config["cpu"] cpu_variant = core_config.get("cpu_variant", "standard") - bus_expose = core_config.get("bus_expose", False) if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 From efad6b3ca523acf99bb75f2307886adb1b988f36 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:54:11 +1000 Subject: [PATCH 2/5] gen: Add option to specify CSR base for standalone cores Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litedram/gen.py b/litedram/gen.py index dab7bcd..8a28413 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -309,11 +309,13 @@ class LiteDRAMCore(SoCCore): kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False + csr_base = core_config.get("csr_base", 0) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, - cpu_type = cpu_type, - cpu_variant = cpu_variant, + cpu_type = cpu_type, + cpu_variant = cpu_variant, + csr_base = csr_base, **kwargs) # CRG -------------------------------------------------------------------------------------- From d5a03b3d89f2542ae9bf090e6070c045efa12ce6 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:54:54 +1000 Subject: [PATCH 3/5] gen: Add option to generate DDRCTL on standalone cores Microwatt will want that as it uses init_done to select whether to run the SDRAM init code or the user code at reset. Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litedram/gen.py b/litedram/gen.py index 8a28413..16fbcb1 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -303,6 +303,7 @@ class LiteDRAMCore(SoCCore): sys_clk_freq = core_config["sys_clk_freq"] cpu_type = core_config["cpu"] cpu_variant = core_config.get("cpu_variant", "standard") + had_ddrctl = core_config.get("has_ddrctl", False) if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 @@ -368,7 +369,7 @@ class LiteDRAMCore(SoCCore): ) # DRAM Control/Status ---------------------------------------------------------------------- - if cpu_type is not None: + if cpu_type is not None or had_ddrctl: # Expose calibration status to user. self.submodules.ddrctrl = LiteDRAMCoreControl() self.add_csr("ddrctrl") @@ -376,7 +377,7 @@ class LiteDRAMCore(SoCCore): platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_error").eq(self.ddrctrl.init_error.storage) ] - else: + if cpu_type is None: # Expose bus interface to user. wb_bus = wishbone.Interface() self.bus.add_master(master=wb_bus) From b0838f70e342fc7a58b3647270b96dc8246767b5 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:58:13 +1000 Subject: [PATCH 4/5] gen: Add option to specify CSR alignment On some standalone core implementations, such with Microwatt, the main system bus is 64-bit, but the wishbone to access the CSRs is 32-bit. To avoid extra logic & muxes and just wire these together, it's useful to be able to specify a larger alignemnt (64-bit) for the CSRs so that the generated csr.h contains the right offsets. Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litedram/gen.py b/litedram/gen.py index 16fbcb1..713914c 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -304,6 +304,7 @@ class LiteDRAMCore(SoCCore): cpu_type = core_config["cpu"] cpu_variant = core_config.get("cpu_variant", "standard") had_ddrctl = core_config.get("has_ddrctl", False) + csr_align = core_config.get("csr_align", 32) if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 @@ -317,6 +318,7 @@ class LiteDRAMCore(SoCCore): cpu_type = cpu_type, cpu_variant = cpu_variant, csr_base = csr_base, + csr_alignment = csr_align, **kwargs) # CRG -------------------------------------------------------------------------------------- From 04717b478bbd835ddbc95badb246a2f923cb8b8d Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:59:01 +1000 Subject: [PATCH 5/5] gen: Rename standalone core wishbone Name it wb_ctrl rather than just wb, which makes the resulting core signal names a bit more descriptive. IE. The DRAM control bus (by opposition to the use/data buss(es). Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litedram/gen.py b/litedram/gen.py index 713914c..7acbaf0 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -381,10 +381,10 @@ class LiteDRAMCore(SoCCore): ] if cpu_type is None: # Expose bus interface to user. - wb_bus = wishbone.Interface() + wb_bus = wishbone.Interface(adr_width = self.csr.address_width) self.bus.add_master(master=wb_bus) - platform.add_extension(wb_bus.get_ios("wb")) - wb_pads = platform.request("wb") + platform.add_extension(wb_bus.get_ios("wb_ctrl")) + wb_pads = platform.request("wb_ctrl") self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave") # User ports -------------------------------------------------------------------------------