diff --git a/litedram/core/bandwidth.py b/litedram/core/bandwidth.py
index 0ac3f22..a39070d 100644
--- a/litedram/core/bandwidth.py
+++ b/litedram/core/bandwidth.py
@@ -14,8 +14,8 @@ from litex.soc.interconnect.csr import *
 class Bandwidth(Module, AutoCSR):
     def __init__(self, cmd, data_width, period_bits=24):
         self.update     = CSR()
-        self.nreads     = CSRStatus(period_bits)
-        self.nwrites    = CSRStatus(period_bits)
+        self.nreads     = CSRStatus(period_bits + 1)
+        self.nwrites    = CSRStatus(period_bits + 1)
         self.data_width = CSRStatus(bits_for(data_width), reset=data_width)
 
         # # #
@@ -33,17 +33,22 @@ class Bandwidth(Module, AutoCSR):
 
         counter   = Signal(period_bits)
         period    = Signal()
-        nreads    = Signal(period_bits)
-        nwrites   = Signal(period_bits)
-        nreads_r  = Signal(period_bits)
-        nwrites_r = Signal(period_bits)
+        nreads    = Signal(period_bits + 1)
+        nwrites   = Signal(period_bits + 1)
+        nreads_r  = Signal(period_bits + 1)
+        nwrites_r = Signal(period_bits + 1)
         self.sync += [
             Cat(counter, period).eq(counter + 1),
             If(period,
                 nreads_r.eq(nreads),
                 nwrites_r.eq(nwrites),
                 nreads.eq(0),
-                nwrites.eq(0)
+                nwrites.eq(0),
+                # don't miss command if there is one on period boundary
+                If(cmd_valid & cmd_ready,
+                    If(cmd_is_read, nreads.eq(1)),
+                    If(cmd_is_write, nwrites.eq(1)),
+                )
             ).Elif(cmd_valid & cmd_ready,
                 If(cmd_is_read, nreads.eq(nreads + 1)),
                 If(cmd_is_write, nwrites.eq(nwrites + 1)),