From f145287fdcd47e3ecda01ef837e52acdef2f888e Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Fri, 5 Jul 2019 09:57:13 +0200 Subject: [PATCH] dma: expose reservation level in the reader --- litedram/frontend/dma.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py index 15e985b..3e6ac0a 100644 --- a/litedram/frontend/dma.py +++ b/litedram/frontend/dma.py @@ -39,6 +39,9 @@ class LiteDRAMDMAReader(Module): source : Record("data") Source for DRAM word results from reading. + + rsv_level: Signal() + FIFO reservation level counter """ def __init__(self, port, fifo_depth=16, fifo_buffered=False): @@ -74,15 +77,15 @@ class LiteDRAMDMAReader(Module): # incremented when data is planned to be queued # decremented when data is dequeued data_dequeued = Signal() - rsv_level = Signal(max=fifo_depth+1) + self.rsv_level = Signal(max=fifo_depth+1) self.sync += [ If(request_issued, - If(~data_dequeued, rsv_level.eq(rsv_level + 1)) + If(~data_dequeued, self.rsv_level.eq(self.rsv_level + 1)) ).Elif(data_dequeued, - rsv_level.eq(rsv_level - 1) + self.rsv_level.eq(self.rsv_level - 1) ) ] - self.comb += request_enable.eq(rsv_level != fifo_depth) + self.comb += request_enable.eq(self.rsv_level != fifo_depth) # FIFO fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered)