diff --git a/test/common.py b/test/common.py index 37eaa81..fab3a70 100644 --- a/test/common.py +++ b/test/common.py @@ -248,6 +248,69 @@ class MemoryTestDataMixin: 0xdeadc0debaadbeef, # 0x38 ], ), + "64bit_to_32bit": dict( + pattern=[ + # address, data + (0x00, 0x0d15ea5e00facade), + (0x05, 0xabadcafe8badf00d), + (0x01, 0xcafefeedbaadf00d), + (0x02, 0xfee1deaddeadc0de), + ], + expected=[ + # data, word, address + 0x00facade, # 0 0x00 + 0x0d15ea5e, # 1 0x04 + 0xbaadf00d, # 2 0x08 + 0xcafefeed, # 3 0x0c + 0xdeadc0de, # 4 0x10 + 0xfee1dead, # 5 0x14 + 0x00000000, # 6 0x18 + 0x00000000, # 7 0x1c + 0x00000000, # 8 0x20 + 0x00000000, # 9 0x24 + 0x8badf00d, # 10 0x28 + 0xabadcafe, # 11 0x2c + 0x00000000, # 12 0x30 + ] + ), + "32bit_to_8bit": dict( + pattern=[ + # address, data + (0x00, 0x00112233), + (0x05, 0x44556677), + (0x01, 0x8899aabb), + (0x02, 0xccddeeff), + ], + expected=[ + # data, address + 0x33, # 0x00 + 0x22, # 0x01 + 0x11, # 0x02 + 0x00, # 0x03 + 0xbb, # 0x04 + 0xaa, # 0x05 + 0x99, # 0x06 + 0x88, # 0x07 + 0xff, # 0x08 + 0xee, # 0x09 + 0xdd, # 0x0a + 0xcc, # 0x0b + 0x00, # 0x0c + 0x00, # 0x0d + 0x00, # 0x0e + 0x00, # 0x0f + 0x00, # 0x10 + 0x00, # 0x11 + 0x00, # 0x12 + 0x00, # 0x13 + 0x77, # 0x14 + 0x66, # 0x15 + 0x55, # 0x16 + 0x44, # 0x17 + 0x00, # 0x18 + 0x00, # 0x19 + ] + ), "32bit_not_aligned": dict( pattern=[ # address, data diff --git a/test/test_wishbone.py b/test/test_wishbone.py index 33528fa..f8df2e6 100644 --- a/test/test_wishbone.py +++ b/test/test_wishbone.py @@ -10,23 +10,24 @@ from litex.soc.interconnect import wishbone from litedram.frontend.wishbone import LiteDRAMWishbone2Native from litedram.common import LiteDRAMNativePort -from test.common import DRAMMemory, seed_to_data +from test.common import DRAMMemory, MemoryTestDataMixin -class TestWishbone(unittest.TestCase): +class TestWishbone(MemoryTestDataMixin, unittest.TestCase): def test_wishbone_data_width_not_smaller(self): with self.assertRaises(AssertionError): wb = wishbone.Interface(data_width=32) port = LiteDRAMNativePort("both", address_width=32, data_width=wb.data_width * 2) LiteDRAMWishbone2Native(wb, port) - def wishbone_readback_test(self, pattern, wishbone, port, mem_depth=64, **kwargs): + def wishbone_readback_test(self, pattern, mem_expected, wishbone, port, base_address=0): class DUT(Module): def __init__(self): self.port = port self.wb = wishbone - self.submodules += LiteDRAMWishbone2Native(self.wb, self.port, **kwargs) - self.mem = DRAMMemory(port.data_width, mem_depth) + self.submodules += LiteDRAMWishbone2Native(self.wb, self.port, + base_address=base_address) + self.mem = DRAMMemory(port.data_width, len(mem_expected)) def main_generator(dut): for adr, data in pattern: @@ -41,14 +42,62 @@ class TestWishbone(unittest.TestCase): dut.mem.read_handler(dut.port), ] run_simulation(dut, generators) - - mem_expected = [0] * mem_depth - for adr, data in pattern: - mem_expected[adr] = data self.assertEqual(dut.mem.mem, mem_expected) - def test_wishbone(self): - pattern = [(adr, seed_to_data(adr, nbits=32)) for adr in range(16)] - wb = wishbone.Interface(data_width=32, adr_width=30) + def test_wishbone_8bit(self): + data = self.pattern_test_data["8bit"] + wb = wishbone.Interface(adr_width=30, data_width=8) + port = LiteDRAMNativePort("both", address_width=30, data_width=8) + self.wishbone_readback_test(data["pattern"], data["expected"], wb, port) + + def test_wishbone_32bit(self): + data = self.pattern_test_data["32bit"] + wb = wishbone.Interface(adr_width=30, data_width=32) port = LiteDRAMNativePort("both", address_width=30, data_width=32) - self.wishbone_readback_test(pattern, wb, port) + self.wishbone_readback_test(data["pattern"], data["expected"], wb, port) + + def test_wishbone_64bit(self): + data = self.pattern_test_data["64bit"] + wb = wishbone.Interface(adr_width=30, data_width=64) + port = LiteDRAMNativePort("both", address_width=30, data_width=64) + self.wishbone_readback_test(data["pattern"], data["expected"], wb, port) + + def test_wishbone_64bit_to_32bit(self): + data = self.pattern_test_data["64bit_to_32bit"] + wb = wishbone.Interface(adr_width=30, data_width=64) + port = LiteDRAMNativePort("both", address_width=30, data_width=32) + self.wishbone_readback_test(data["pattern"], data["expected"], wb, port) + + def test_wishbone_32bit_to_8bit(self): + data = self.pattern_test_data["32bit_to_8bit"] + wb = wishbone.Interface(adr_width=30, data_width=32) + port = LiteDRAMNativePort("both", address_width=30, data_width=8) + self.wishbone_readback_test(data["pattern"], data["expected"], wb, port) + + def test_wishbone_32bit_base_address(self): + data = self.pattern_test_data["32bit"] + wb = wishbone.Interface(adr_width=30, data_width=32) + port = LiteDRAMNativePort("both", address_width=30, data_width=32) + origin = 0x10000000 + # add offset (in data words) + pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]] + self.wishbone_readback_test(pattern, data["expected"], wb, port, + base_address=origin) + + def test_wishbone_64bit_to_32bit_base_address(self): + data = self.pattern_test_data["64bit_to_32bit"] + wb = wishbone.Interface(adr_width=30, data_width=64) + port = LiteDRAMNativePort("both", address_width=30, data_width=32) + origin = 0x10000000 + pattern = [(adr + origin//(64//8), data) for adr, data in data["pattern"]] + self.wishbone_readback_test(pattern, data["expected"], wb, port, + base_address=origin) + + def test_wishbone_32bit_to_8bit_base_address(self): + data = self.pattern_test_data["32bit_to_8bit"] + wb = wishbone.Interface(adr_width=30, data_width=32) + port = LiteDRAMNativePort("both", address_width=30, data_width=8) + origin = 0x10000000 + pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]] + self.wishbone_readback_test(pattern, data["expected"], wb, port, + base_address=origin)