From f1a40cef2f0980f8f9564c52eea22ccaa681b2c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 16 Mar 2021 13:12:27 +0100 Subject: [PATCH] core: use wider DFI address/bank if PHY requires it --- litedram/core/__init__.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litedram/core/__init__.py b/litedram/core/__init__.py index 4e624de..715eefc 100644 --- a/litedram/core/__init__.py +++ b/litedram/core/__init__.py @@ -17,8 +17,8 @@ from litedram.core.crossbar import LiteDRAMCrossbar class LiteDRAMCore(Module, AutoCSR): def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs): self.submodules.dfii = DFIInjector( - addressbits = geom_settings.addressbits, - bankbits = geom_settings.bankbits, + addressbits = max(geom_settings.addressbits, getattr(phy, "addressbits", 0)), + bankbits = max(geom_settings.bankbits, getattr(phy, "bankbits", 0)), nranks = phy.settings.nranks, databits = phy.settings.dfi_databits, nphases = phy.settings.nphases)