diff --git a/litedram/phy/k7ddrphy.py b/litedram/phy/k7ddrphy.py
index 3ccb7f0..aea75b2 100644
--- a/litedram/phy/k7ddrphy.py
+++ b/litedram/phy/k7ddrphy.py
@@ -18,10 +18,13 @@ class K7DDRPHY(Module, AutoCSR):
 
         self._wlevel_en = CSRStorage()
         self._wlevel_strobe = CSR()
+
         self._dly_sel = CSRStorage(databits//8)
+
         self._rdly_dq_rst = CSR()
         self._rdly_dq_inc = CSR()
         self._rdly_dq_bitslip = CSR()
+
         self._wdly_dq_rst = CSR()
         self._wdly_dq_inc = CSR()
         self._wdly_dqs_rst = CSR()
diff --git a/litedram/phy/kusddrphy.py b/litedram/phy/kusddrphy.py
index ad94733..2374749 100644
--- a/litedram/phy/kusddrphy.py
+++ b/litedram/phy/kusddrphy.py
@@ -24,7 +24,7 @@ class KUSDDRPHY(Module, AutoCSR):
 
         self._rdly_dq_rst = CSR()
         self._rdly_dq_inc = CSR()
-        self._rdly_dq_bitslip = CSRStorage(3)
+        self._rdly_dq_bitslip = CSR()
 
         self._wdly_dq_rst = CSR()
         self._wdly_dq_inc = CSR()
@@ -200,7 +200,11 @@ class KUSDDRPHY(Module, AutoCSR):
             dq_bitslip = BitSlip(8)
             self.sync += \
                 If(self._dly_sel.storage[i//8],
-                    dq_bitslip.value.eq(self._rdly_dq_bitslip.storage)
+                    If(self._rdly_dq_rst.re,
+                        dq_bitslip.value.eq(0)
+                    ).Elif(self._rdly_dq_bitslip.re,
+                        dq_bitslip.value.eq(dq_bitslip.value + 1)
+                    )
                 )
             self.submodules += dq_bitslip
             self.specials += [