diff --git a/litedram/phy/lpddr4/basephy.py b/litedram/phy/lpddr4/basephy.py
index 8a178b0..978401b 100644
--- a/litedram/phy/lpddr4/basephy.py
+++ b/litedram/phy/lpddr4/basephy.py
@@ -122,7 +122,7 @@ class LPDDR4PHY(Module, AutoCSR):
         bitslip_cycles  = 1
         bitslip_range   = 1
         # Commands are sent over 4 DRAM clocks (sys8x) and we count cl/cwl from last bit
-        cmd_latency     = 4  # FIXME: or should it be 3?
+        cmd_latency     = 4
         # Commands read from adapters are delayed on ConstBitSlips
         ca_latency      = 1
 
diff --git a/litedram/phy/lpddr4/utils.py b/litedram/phy/lpddr4/utils.py
index b6aa0ea..68ef46a 100644
--- a/litedram/phy/lpddr4/utils.py
+++ b/litedram/phy/lpddr4/utils.py
@@ -61,8 +61,7 @@ class DQSPattern(Module):
         self.comb += [
             self.o.eq(0b0101010101010101),
             If(self.preamble,
-                # FIXME: using 2tCK write preamble, but it depends on mode registers
-                self.o.eq(0b0101000001010101)
+                self.o.eq(0b0101000001010101)  # 2tCK write preamble
             ),
             If(self.postamble,
                 self.o.eq(0b0101010101010100)