From f31f8a03ff6911befa6d07bf347f8478c30448d8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 25 Jul 2017 10:34:03 +0200 Subject: [PATCH] modules: add MT46H32M32 --- litedram/modules.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/litedram/modules.py b/litedram/modules.py index b22b96e..ea4d9be 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -112,6 +112,20 @@ class MT46H32M16(SDRAMModule): tREFI = 64*1000*1000/8192 tRFC = 72 +class MT46H32M32(SDRAMModule): + memtype = "LPDDR" + # geometry + nbanks = 4 + nrows = 8192 + ncols = 1024 + # timings + tRP = 15 + tRCD = 15 + tWR = 15 + tWTR = 2 + tREFI = 64*1000*1000/8192 + tRFC = 72 + # DDR2 class MT47H128M8(SDRAMModule):