From f36c65b66f8fd00c906f6f4fd9a2e7ea10947039 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 23 May 2016 13:30:38 +0200
Subject: [PATCH] test: move DRAMMemory model to common

---
 test/bist_tb.py | 56 ++-----------------------------------------------
 test/common.py  | 53 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 54 deletions(-)
 create mode 100644 test/common.py

diff --git a/test/bist_tb.py b/test/bist_tb.py
index 291f82d..d081e4c 100644
--- a/test/bist_tb.py
+++ b/test/bist_tb.py
@@ -6,6 +6,8 @@ from litedram.common import LiteDRAMPort
 from litedram.frontend.bist import LiteDRAMBISTGenerator
 from litedram.frontend.bist import LiteDRAMBISTChecker
 
+from test.common import DRAMMemory
+
 class TB(Module):
     def __init__(self):
         self.write_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
@@ -13,60 +15,6 @@ class TB(Module):
         self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
         self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
 
-
-class DRAMMemory:
-    def __init__(self, width, depth, init=[]):
-        self.width = width
-        self.depth = depth
-        self.mem = []
-        for d in init:
-            self.mem.append(d)
-        for _ in range(depth-len(init)):
-            self.mem.append(0)
-
-    @passive
-    def read_generator(self, dram_port):
-        address = 0
-        pending = 0
-        while True:
-            yield dram_port.cmd.ready.eq(0)
-            yield dram_port.rdata.valid.eq(0)
-            if pending:
-                yield dram_port.rdata.valid.eq(1)
-                yield dram_port.rdata.data.eq(self.mem[address%self.depth])
-                yield
-                yield dram_port.rdata.valid.eq(0)
-                yield dram_port.rdata.data.eq(0)
-                pending = 0
-            elif (yield dram_port.cmd.valid):
-                pending = not (yield dram_port.cmd.we)
-                address = (yield dram_port.cmd.adr)
-                yield
-                yield dram_port.cmd.ready.eq(1)
-            yield
-
-    @passive
-    def write_generator(self, dram_port):
-        address = 0
-        pending = 0
-        while True:
-            yield dram_port.cmd.ready.eq(0)
-            yield dram_port.wdata.ready.eq(0)
-            if pending:
-                yield dram_port.wdata.ready.eq(1)
-                yield
-                self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
-                yield dram_port.wdata.ready.eq(0)
-                yield
-                pending = 0
-            elif (yield dram_port.cmd.valid):
-                pending = yield dram_port.cmd.we
-                address = (yield dram_port.cmd.adr)
-                yield
-                yield dram_port.cmd.ready.eq(1)
-            yield
-
-
 def main_generator(dut):
     for i in range(100):
         yield
diff --git a/test/common.py b/test/common.py
new file mode 100644
index 0000000..dfc30f9
--- /dev/null
+++ b/test/common.py
@@ -0,0 +1,53 @@
+from litex.gen import *
+
+class DRAMMemory:
+    def __init__(self, width, depth, init=[]):
+        self.width = width
+        self.depth = depth
+        self.mem = []
+        for d in init:
+            self.mem.append(d)
+        for _ in range(depth-len(init)):
+            self.mem.append(0)
+
+    @passive
+    def read_generator(self, dram_port):
+        address = 0
+        pending = 0
+        while True:
+            yield dram_port.cmd.ready.eq(0)
+            yield dram_port.rdata.valid.eq(0)
+            if pending:
+                yield dram_port.rdata.valid.eq(1)
+                yield dram_port.rdata.data.eq(self.mem[address%self.depth])
+                yield
+                yield dram_port.rdata.valid.eq(0)
+                yield dram_port.rdata.data.eq(0)
+                pending = 0
+            elif (yield dram_port.cmd.valid):
+                pending = not (yield dram_port.cmd.we)
+                address = (yield dram_port.cmd.adr)
+                yield
+                yield dram_port.cmd.ready.eq(1)
+            yield
+
+    @passive
+    def write_generator(self, dram_port):
+        address = 0
+        pending = 0
+        while True:
+            yield dram_port.cmd.ready.eq(0)
+            yield dram_port.wdata.ready.eq(0)
+            if pending:
+                yield dram_port.wdata.ready.eq(1)
+                yield
+                self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
+                yield dram_port.wdata.ready.eq(0)
+                yield
+                pending = 0
+            elif (yield dram_port.cmd.valid):
+                pending = yield dram_port.cmd.we
+                address = (yield dram_port.cmd.adr)
+                yield
+                yield dram_port.cmd.ready.eq(1)
+            yield