diff --git a/litedram/common.py b/litedram/common.py
index 0cccc9b..321afa3 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -38,8 +38,27 @@ class TimingSettings:
         self.tREFI = tREFI
         self.tRFC = tRFC
 
+def cmd_layout(aw):
+    return [
+        ("valid",      1, DIR_M_TO_S),
+        ("ready",      1, DIR_S_TO_M),
+        ("we",         1, DIR_M_TO_S),
+        ("adr",       aw, DIR_M_TO_S),
+        ("dat_w_ack",  1, DIR_S_TO_M),
+        ("dat_r_ack",  1, DIR_S_TO_M),
+        ("lock",       1, DIR_S_TO_M)
+    ]
 
-class Interface(Record):
+
+def data_layout(dw):
+    return [
+        ("dat_w",     dw, DIR_M_TO_S),
+        ("dat_we", dw//8, DIR_M_TO_S),
+        ("dat_r",     dw, DIR_S_TO_M)
+    ]
+
+
+class InternalInterface(Record):
     def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
         self.aw = aw
         self.dw = dw
@@ -48,24 +67,20 @@ class Interface(Record):
         self.read_latency = read_latency
         self.write_latency = write_latency
 
-        bank_layout = [
-            ("valid",     1, DIR_M_TO_S),
-            ("ready",     1, DIR_S_TO_M),
-            ("we",        1, DIR_M_TO_S),
-            ("adr",      aw, DIR_M_TO_S),
-            ("dat_w_ack", 1, DIR_S_TO_M),
-            ("dat_r_ack", 1, DIR_S_TO_M),
-            ("lock",      1, DIR_S_TO_M)
-        ]
-        if nbanks > 1:
-            layout = [("bank"+str(i), bank_layout) for i in range(nbanks)]
-        else:
-            layout = bank_layout
-        layout += [
-            ("dat_w",     dw, DIR_M_TO_S),
-            ("dat_we", dw//8, DIR_M_TO_S),
-            ("dat_r",     dw, DIR_S_TO_M)
-        ]
+        layout = [("bank"+str(i), cmd_layout(aw)) for i in range(nbanks)]
+        layout += data_layout(dw)
+        Record.__init__(self, layout)
+
+
+class UserInterface(Record):
+    def __init__(self, aw, dw, req_queue_size, read_latency, write_latency):
+        self.aw = aw
+        self.dw = dw
+        self.req_queue_size = req_queue_size
+        self.read_latency = read_latency
+        self.write_latency = write_latency
+
+        layout = cmd_layout(aw) + data_layout(dw)
         Record.__init__(self, layout)
 
 
diff --git a/litedram/core/controller.py b/litedram/core/controller.py
index fa45a9c..ba9a8ca 100644
--- a/litedram/core/controller.py
+++ b/litedram/core/controller.py
@@ -34,7 +34,7 @@ class LiteDRAMController(Module):
             phy_settings.dfi_databits,
             phy_settings.nphases)
 
-        self.lasmic = common.Interface(
+        self.lasmic = common.InternalInterface(
             aw=geom_settings.rowbits + geom_settings.colbits - address_align,
             dw=phy_settings.dfi_databits*phy_settings.nphases,
             nbanks=2**geom_settings.bankbits,
diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py
index 100045f..a038ba7 100644
--- a/litedram/frontend/crossbar.py
+++ b/litedram/frontend/crossbar.py
@@ -26,8 +26,8 @@ class LiteDRAMCrossbar(Module):
     def get_port(self):
         if self.finalized:
             raise FinalizeError
-        port = Interface(self.rca_bits + self.bank_bits,
-            self.dw, 1, self.req_queue_size, self.read_latency, self.write_latency)
+        port = UserInterface(self.rca_bits + self.bank_bits,
+            self.dw, self.req_queue_size, self.read_latency, self.write_latency)
         self.masters.append(port)
         return port