From f39625372901a5fbbfb4311e2e08c096a919ec7b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 11 Apr 2022 17:49:19 +0200 Subject: [PATCH] frontend/axi/rmw: Fix simulation mismatch between unit-test/verilator. --- litedram/frontend/axi.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litedram/frontend/axi.py b/litedram/frontend/axi.py index a5514b1..956eaae 100644 --- a/litedram/frontend/axi.py +++ b/litedram/frontend/axi.py @@ -116,8 +116,9 @@ class LiteDRAMAXI2NativeW(Module): ] # Write Data ------------------------------------------------------------------------------- + axi_w_connect = Signal(reset=1) self.comb += [ - axi.w.connect(w_buffer.sink), + If(axi_w_connect, axi.w.connect(w_buffer.sink)), w_buffer.source.connect(port.wdata, omit={"strb", "id"}), port.wdata.we.eq(w_buffer.source.strb) ] @@ -146,8 +147,7 @@ class LiteDRAMAXI2NativeW(Module): # Disconnect regular Datapath on a Read-Modify-Write cycle. self.comb += If(self.rmw_request, - axi.w.ready.eq(0), - w_buffer.sink.valid.eq(0) + axi_w_connect.eq(0), ) # Read-Modify-Write FSM. @@ -185,7 +185,7 @@ class LiteDRAMAXI2NativeW(Module): port.rdata.ready.eq(1), If(port.rdata.valid, # Keep previous unmasked data and replace masked data with new ones. - NextValue(rmw_data, (port.rdata.data & (~rmw_mask) | (axi.w.data & rmw_mask))), + NextValue(rmw_data, (port.rdata.data & ~rmw_mask) | (axi.w.data & rmw_mask)), NextState("WRITE") ) )