diff --git a/examples/arty_config.py b/examples/arty_config.py index 8ed4b75..1bf8762 100644 --- a/examples/arty_config.py +++ b/examples/arty_config.py @@ -2,33 +2,33 @@ from litedram.modules import MT41K128M16 from litedram.phy import A7DDRPHY core_config = { - # cpu - "cpu": "picorv32", + # General ------------------------------------------------------------------ + "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) + "speedgrade": -1, # FPGA speedgrade - # modules / phy - "sdram_module": MT41K128M16, - "sdram_module_nb": 1, - "sdram_module_speedgrade": "800", - "sdram_rank_nb": 1, - "sdram_phy": A7DDRPHY, + # PHY ---------------------------------------------------------------------- + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": MT41K128M16, # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": A7DDRPHY, # Type of FPGA PHY - # electrical - "rtt_nom": "60ohm", - "rtt_wr": "60ohm", - "ron": "34ohm", + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance - # freqs - "input_clk_freq": 100e6, - "sys_clk_freq": 100e6, - "iodelay_clk_freq": 200e6, + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 100e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency - # controller - "cmd_buffer_depth": 16, - "write_time": 16, - "read_time": 32, + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer - # user_ports - "user_ports_nb": 1, - "user_ports_type": "axi", - "user_ports_id_width": 8 + # User Ports --------------------------------------------------------------- + "user_ports_nb": 2, # Number of user ports + "user_ports_type": "axi", # Type of ports (axi, native) + "user_ports_id_width": 32, # AXI identifier width } diff --git a/examples/genesys2_config.py b/examples/genesys2_config.py index 2ad175d..89dda56 100644 --- a/examples/genesys2_config.py +++ b/examples/genesys2_config.py @@ -2,33 +2,33 @@ from litedram.modules import MT41J256M16 from litedram.phy import K7DDRPHY core_config = { - # cpu - "cpu": "picorv32", + # General ------------------------------------------------------------------ + "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) + "speedgrade": -2, # FPGA speedgrade - # modules / phy - "sdram_module": MT41J256M16, - "sdram_module_nb": 2, - "sdram_module_speedgrade": "1333", - "sdram_rank_nb": 1, - "sdram_phy": K7DDRPHY, + # PHY ---------------------------------------------------------------------- + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": MT41J256M16, # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 4, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": K7DDRPHY, # Type of FPGA PHY - # electrical - "rtt_nom": "60ohm", - "rtt_wr": "60ohm", - "ron": "34ohm", + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance - # freqs - "input_clk_freq": 200e6, - "sys_clk_freq": 125e6, - "iodelay_clk_freq": 200e6, + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 200e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency - # controller - "cmd_buffer_depth": 16, - "write_time": 16, - "read_time": 32, + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer - # user_ports - "user_ports_nb": 1, - "user_ports_type": "axi", - "user_ports_id_width": 8 + # User Ports --------------------------------------------------------------- + "user_ports_nb": 2, # Number of user ports + "user_ports_type": "axi", # Type of ports (axi, native) + "user_ports_id_width": 32, # AXI identifier width } diff --git a/examples/litedram_gen.py b/examples/litedram_gen.py index d38baa9..f3b8cbe 100755 --- a/examples/litedram_gen.py +++ b/examples/litedram_gen.py @@ -59,10 +59,10 @@ def get_dram_ios(core_config): Subsignal("cas_n", Pins(1)), Subsignal("we_n", Pins(1)), Subsignal("cs_n", Pins(core_config["sdram_rank_nb"])), - Subsignal("dm", Pins(2*core_config["sdram_module_nb"])), - Subsignal("dq", Pins(16*core_config["sdram_module_nb"])), - Subsignal("dqs_p", Pins(2*core_config["sdram_module_nb"])), - Subsignal("dqs_n", Pins(2*core_config["sdram_module_nb"])), + Subsignal("dm", Pins(core_config["sdram_module_nb"])), + Subsignal("dq", Pins(8*core_config["sdram_module_nb"])), + Subsignal("dqs_p", Pins(core_config["sdram_module_nb"])), + Subsignal("dqs_n", Pins(core_config["sdram_module_nb"])), Subsignal("clk_p", Pins(core_config["sdram_rank_nb"])), Subsignal("clk_n", Pins(core_config["sdram_rank_nb"])), Subsignal("cke", Pins(core_config["sdram_rank_nb"])), @@ -93,6 +93,7 @@ def get_native_user_port_ios(_id, aw, dw): ), ] + def get_axi_user_port_ios(_id, aw, dw, iw): return [ ("user_port", _id, @@ -152,15 +153,22 @@ class LiteDRAMCRG(Module): # # # - self.submodules.pll = pll = S7PLL() - self.comb += pll.reset.eq(platform.request("rst")) - pll.register_clkin(platform.request("clk"), core_config["input_clk_freq"]) - pll.create_clkout(self.cd_sys, core_config["sys_clk_freq"]) - pll.create_clkout(self.cd_sys4x, 4*core_config["sys_clk_freq"]) - pll.create_clkout(self.cd_sys4x_dqs, 4*core_config["sys_clk_freq"], phase=90) - pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"]) + clk = platform.request("clk") + rst = platform.request("rst") + + self.submodules.sys_pll = sys_pll = S7PLL(speedgrade=core_config["speedgrade"]) + self.comb += sys_pll.reset.eq(rst) + sys_pll.register_clkin(clk, core_config["input_clk_freq"]) + sys_pll.create_clkout(self.cd_sys, core_config["sys_clk_freq"]) + sys_pll.create_clkout(self.cd_sys4x, 4*core_config["sys_clk_freq"]) + sys_pll.create_clkout(self.cd_sys4x_dqs, 4*core_config["sys_clk_freq"], phase=90) + self.comb += platform.request("pll_locked").eq(sys_pll.locked) + + self.submodules.iodelay_pll = iodelay_pll = S7PLL() + self.comb += iodelay_pll.reset.eq(rst) + iodelay_pll.register_clkin(clk, core_config["input_clk_freq"]) + iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"]) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay) - self.comb += platform.request("pll_locked").eq(pll.locked) class LiteDRAMCoreControl(Module, AutoCSR): @@ -180,12 +188,8 @@ class LiteDRAMCore(SoCSDRAM): sys_clk_freq = core_config["sys_clk_freq"] SoCSDRAM.__init__(self, platform, sys_clk_freq, cpu_type=core_config["cpu"], - l2_size=32*core_config["sdram_module_nb"], + l2_size=16*core_config["sdram_module_nb"], reserve_nmi_interrupt=False, - csr_data_width=8 if core_config["cpu"] is not None else 32, - with_uart=core_config["cpu"] is not None, - with_timer=core_config["cpu"] is not None, - csr_expose=True, **kwargs) # crg @@ -193,17 +197,19 @@ class LiteDRAMCore(SoCSDRAM): # sdram platform.add_extension(get_dram_ios(core_config)) - self.submodules.ddrphy = core_config["sdram_phy"](platform.request("ddram"), sys_clk_freq=sys_clk_freq, - iodelay_clk_freq=core_config["iodelay_clk_freq"]) + self.submodules.ddrphy = core_config["sdram_phy"]( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq, + iodelay_clk_freq=core_config["iodelay_clk_freq"], + cmd_latency=core_config["cmd_latency"]) + self.add_constant("CMD_DELAY", core_config["cmd_delay"]) self.ddrphy.settings.add_electrical_settings( rtt_nom=core_config["rtt_nom"], rtt_wr=core_config["rtt_wr"], ron=core_config["ron"]) - sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4", speedgrade=core_config["sdram_module_speedgrade"]) + sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4") controller_settings = controller_settings=ControllerSettings( - cmd_buffer_depth=core_config["cmd_buffer_depth"], - read_time=core_config["read_time"], - write_time=core_config["write_time"]) + cmd_buffer_depth=core_config["cmd_buffer_depth"]) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, @@ -211,7 +217,6 @@ class LiteDRAMCore(SoCSDRAM): # sdram init self.submodules.ddrctrl = LiteDRAMCoreControl() - self.add_constant("DDRPHY_HIGH_SKEW_DISABLE", None) self.comb += [ platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_error").eq(self.ddrctrl.init_error.storage)