From f466c5f1dbeb37c4dde8471c5422ce6d2175c414 Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Wed, 11 Jan 2023 14:19:31 +0100 Subject: [PATCH] frontend/bist: replicate LFSR output to fill DRAM port Signed-off-by: Michal Sieron --- litedram/frontend/bist.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index 099887f..3414e91 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -8,6 +8,7 @@ """Built In Self Test (BIST) modules for testing LiteDRAM functionality.""" from functools import reduce +from math import ceil from operator import xor from migen import * @@ -211,7 +212,12 @@ class _LiteDRAMBISTGenerator(Module): raise NotImplementedError self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask)) - self.comb += dma.sink.data.eq(data_gen.o) + self.comb += dma.sink.data.eq( + Replicate( + data_gen.o, + ceil(dram_port.data_width / len(data_gen.o)), + )[:dram_port.data_width], + ) @ResetInserter() @@ -511,7 +517,10 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): If(dma.source.valid, data_gen.ce.eq(1), NextValue(data_counter, data_counter + 1), - If(dma.source.data != data_gen.o[:min(len(data_gen.o), dram_port.data_width)], + If(dma.source.data != Replicate( + data_gen.o, + ceil(dram_port.data_width / len(data_gen.o)), + )[:dram_port.data_width], NextValue(self.errors, self.errors + 1) ), If(data_counter == (self.length[ashift:] - 1),