From f4de17b8e6fdc4ad7939d7e619016d621a77f7a6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 25 Jan 2020 17:00:18 +0100 Subject: [PATCH] phy/ecp5ddrphy: reorder signals/parameters on primitives --- litedram/phy/ecp5ddrphy.py | 78 +++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py index 7e78daf..930f41f 100644 --- a/litedram/phy/ecp5ddrphy.py +++ b/litedram/phy/ecp5ddrphy.py @@ -142,37 +142,37 @@ class ECP5DDRPHY(Module, AutoCSR): for i in range(len(pads.clk_p)): sd_clk_se = Signal() self.specials += Instance("ODDRX2F", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), i_D0 = 0, i_D1 = 1, i_D2 = 0, i_D3 = 1, - i_ECLK = ClockSignal("sys2x"), - i_SCLK = ClockSignal(), - i_RST = ResetSignal("sys2x"), o_Q = pads.clk_p[i] ) # Addresses and Commands ------------------------------------------------------------------- for i in range(addressbits): self.specials += Instance("ODDRX2F", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), i_D0 = dfi.phases[0].address[i], i_D1 = dfi.phases[0].address[i], i_D2 = dfi.phases[1].address[i], i_D3 = dfi.phases[1].address[i], - i_ECLK = ClockSignal("sys2x"), - i_SCLK = ClockSignal(), - i_RST = ResetSignal("sys2x"), o_Q = pads.a[i] ) for i in range(bankbits): self.specials += Instance("ODDRX2F", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), i_D0 = dfi.phases[0].bank[i], i_D1 = dfi.phases[0].bank[i], i_D2 = dfi.phases[1].bank[i], i_D3 = dfi.phases[1].bank[i], - i_ECLK = ClockSignal("sys2x"), - i_SCLK = ClockSignal(), - i_RST = ResetSignal("sys2x"), o_Q = pads.ba[i] ) controls = ["ras_n", "cas_n", "we_n", "cke", "odt"] @@ -183,13 +183,13 @@ class ECP5DDRPHY(Module, AutoCSR): for name in controls: for i in range(len(getattr(pads, name))): self.specials += Instance("ODDRX2F", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), i_D0 = getattr(dfi.phases[0], name)[i], i_D1 = getattr(dfi.phases[0], name)[i], i_D2 = getattr(dfi.phases[1], name)[i], i_D3 = getattr(dfi.phases[1], name)[i], - i_ECLK = ClockSignal("sys2x"), - i_SCLK = ClockSignal(), - i_RST = ResetSignal("sys2x"), o_Q = getattr(pads, name)[i] ) @@ -289,14 +289,14 @@ class ECP5DDRPHY(Module, AutoCSR): dm_o_data_muxed.eq(dm_o_data[:4]) ) self.specials += Instance("ODDRX2DQA", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), + i_DQSW270 = dqsw270, i_D0 = dm_o_data_muxed[0], i_D1 = dm_o_data_muxed[1], i_D2 = dm_o_data_muxed[2], i_D3 = dm_o_data_muxed[3], - i_RST = ResetSignal("sys2x"), - i_DQSW270 = dqsw270, - i_ECLK = ClockSignal("sys2x"), - i_SCLK = ClockSignal(), o_Q = pads.dm[i] ) @@ -304,24 +304,24 @@ class ECP5DDRPHY(Module, AutoCSR): dqs_oe_n = Signal() self.specials += [ Instance("ODDRX2DQSB", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), + i_DQSW = dqsw, i_D0 = dqs_serdes_pattern[0], i_D1 = dqs_serdes_pattern[1], i_D2 = dqs_serdes_pattern[2], i_D3 = dqs_serdes_pattern[3], - i_RST = ResetSignal("sys2x"), - i_DQSW = dqsw, - i_ECLK = ClockSignal("sys2x"), - i_SCLK = ClockSignal(), o_Q = dqs ), Instance("TSHX2DQSA", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), + i_DQSW = dqsw, i_T0 = ~(oe_dqs|dqs_postamble), i_T1 = ~(oe_dqs|dqs_preamble), - i_SCLK = ClockSignal(), - i_ECLK = ClockSignal("sys2x"), - i_DQSW = dqsw, - i_RST = ResetSignal("sys2x"), - o_Q = dqs_oe_n, + o_Q = dqs_oe_n ), Tristate(pads.dqs_p[i], dqs, ~dqs_oe_n, dqs_i) ] @@ -350,36 +350,36 @@ class ECP5DDRPHY(Module, AutoCSR): ) self.specials += [ Instance("ODDRX2DQA", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), + i_DQSW270 = dqsw270, i_D0 = dq_o_data_muxed[0], i_D1 = dq_o_data_muxed[1], i_D2 = dq_o_data_muxed[2], i_D3 = dq_o_data_muxed[3], - i_RST = ResetSignal("sys2x"), - i_DQSW270 = dqsw270, - i_ECLK = ClockSignal("sys2x"), - i_SCLK = ClockSignal(), o_Q = dq_o ), Instance("DELAYF", - i_A = dq_i, + p_DEL_MODE = "DQS_ALIGNED_X2", i_LOADN = 1, i_MOVE = 0, i_DIRECTION = 0, - o_Z = dq_i_delayed, - p_DEL_MODE = "DQS_ALIGNED_X2" + i_A = dq_i, + o_Z = dq_i_delayed ), Instance("IDDRX2DQA", - i_D = dq_i_delayed, i_RST = ResetSignal("sys2x"), - i_DQSR90 = dqsr90, - i_SCLK = ClockSignal(), i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), + i_DQSR90 = dqsr90, i_RDPNTR0 = rdpntr[0], i_RDPNTR1 = rdpntr[1], i_RDPNTR2 = rdpntr[2], i_WRPNTR0 = wrpntr[0], i_WRPNTR1 = wrpntr[1], i_WRPNTR2 = wrpntr[2], + i_D = dq_i_delayed, o_Q0 = dq_i_data[0], o_Q1 = dq_i_data[1], o_Q2 = dq_i_data[2], @@ -407,12 +407,12 @@ class ECP5DDRPHY(Module, AutoCSR): ] self.specials += [ Instance("TSHX2DQA", + i_RST = ResetSignal("sys2x"), + i_ECLK = ClockSignal("sys2x"), + i_SCLK = ClockSignal(), + i_DQSW270 = dqsw270, i_T0 = ~oe_dq, i_T1 = ~oe_dq, - i_SCLK = ClockSignal(), - i_ECLK = ClockSignal("sys2x"), - i_DQSW270 = dqsw270, - i_RST = ResetSignal("sys2x"), o_Q = dq_oe_n, ), Tristate(pads.dq[j], dq_o, ~dq_oe_n, dq_i)