diff --git a/litedram/core/controller.py b/litedram/core/controller.py
index e4b18d7..2f043f5 100644
--- a/litedram/core/controller.py
+++ b/litedram/core/controller.py
@@ -45,7 +45,10 @@ class ControllerSettings(Settings):
 class LiteDRAMController(Module):
     def __init__(self, phy_settings, geom_settings, timing_settings, clk_freq,
         controller_settings=ControllerSettings()):
-        burst_length = phy_settings.nphases * (1 if phy_settings.memtype == "SDR" else 2)
+        if phy_settings.memtype == "SDR":
+            burst_length = phy_settings.nphases
+        else:
+            burst_length = burst_lengths[phy_settings.memtype]
         address_align = log2_int(burst_length)
 
         # Settings ---------------------------------------------------------------------------------