From f560b9c182a1aded009ab8c47e3b94726ba6aeed Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 19 Jul 2018 15:22:45 +0200
Subject: [PATCH] core/bankmachine: remove auto-prechage since introducing a
 regression, we'll need to do more simulation before integrating

---
 litedram/core/bankmachine.py | 59 +++++++++++-------------------------
 1 file changed, 18 insertions(+), 41 deletions(-)

diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py
index 28e5904..da026eb 100644
--- a/litedram/core/bankmachine.py
+++ b/litedram/core/bankmachine.py
@@ -37,27 +37,25 @@ class BankMachine(Module):
 
         # # #
 
-        slicer = _AddressSlicer(settings.geom.colbits, address_align)
-
         # Command buffer
         cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))]
-        cmd_buffer0 = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth-1)
-        cmd_buffer1 = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change
-        self.submodules += cmd_buffer0, cmd_buffer1
+        cmd_buffer = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
+        self.submodules += cmd_buffer
         self.comb += [
-            req.connect(cmd_buffer0.sink, omit=["wdata_valid", "wdata_ready",
-                                                "rdata_valid", "rdata_ready",
-                                                "lock"]),
-            cmd_buffer0.source.connect(cmd_buffer1.sink),
-            cmd_buffer1.source.ready.eq(req.wdata_ready | req.rdata_valid),
-            req.lock.eq(cmd_buffer1.source.valid),
+            req.connect(cmd_buffer.sink, omit=["wdata_valid", "wdata_ready",
+                                               "rdata_valid", "rdata_ready",
+                                               "lock"]),
+            cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid),
+            req.lock.eq(cmd_buffer.source.valid),
         ]
 
+        slicer = _AddressSlicer(settings.geom.colbits, address_align)
+
         # Row tracking
         has_openrow = Signal()
         openrow = Signal(settings.geom.rowbits, reset_less=True)
         hit = Signal()
-        self.comb += hit.eq(openrow == slicer.row(cmd_buffer1.source.adr))
+        self.comb += hit.eq(openrow == slicer.row(cmd_buffer.source.adr))
         track_open = Signal()
         track_close = Signal()
         self.sync += \
@@ -65,20 +63,9 @@ class BankMachine(Module):
                 has_openrow.eq(0)
             ).Elif(track_open,
                 has_openrow.eq(1),
-                openrow.eq(slicer.row(cmd_buffer1.source.adr))
+                openrow.eq(slicer.row(cmd_buffer.source.adr))
             )
 
-        # Auto Precharge
-        auto_precharge = Signal()
-        self.comb += [
-            # If both buffers have data to output, check row to see
-            # if we can embed an autoprecharge in current cmd.
-            If(cmd_buffer0.source.valid & cmd_buffer1.source.valid,
-                If(slicer.row(cmd_buffer0.source.adr) != slicer.row(cmd_buffer1.source.adr),
-                    auto_precharge.eq((track_close == 0))
-                )
-            )
-        ]
 
         # Four Activate Window
         activate = Signal()
@@ -113,9 +100,9 @@ class BankMachine(Module):
         self.comb += [
             cmd.ba.eq(n),
             If(sel_row_adr,
-                cmd.a.eq(slicer.row(cmd_buffer1.source.adr))
+                cmd.a.eq(slicer.row(cmd_buffer.source.adr))
             ).Else(
-                cmd.a.eq((auto_precharge << 10) | slicer.col(cmd_buffer1.source.adr))
+                cmd.a.eq(slicer.col(cmd_buffer.source.adr))
             )
         ]
 
@@ -131,7 +118,7 @@ class BankMachine(Module):
         fsm.act("REGULAR",
             If(self.refresh_req,
                 NextState("REFRESH")
-            ).Elif(cmd_buffer1.source.valid,
+            ).Elif(cmd_buffer.source.valid,
                 If(has_openrow,
                     If(hit,
                         If(cas_allowed,
@@ -139,7 +126,7 @@ class BankMachine(Module):
                             # Note: write-to-read specification is enforced by
                             # multiplexer
                             cmd.valid.eq(1),
-                            If(cmd_buffer1.source.we,
+                            If(cmd_buffer.source.we,
                                 req.wdata_ready.eq(cmd.ready),
                                 cmd.is_write.eq(1),
                                 cmd.we.eq(1),
@@ -147,13 +134,10 @@ class BankMachine(Module):
                                 req.rdata_valid.eq(cmd.ready),
                                 cmd.is_read.eq(1)
                             ),
-                            cmd.cas.eq(1),
-                            If(cmd.ready & auto_precharge,
-                                NextState("AUTOPRECHARGE")
-                            )
-                        ).Else(
-                            NextState("PRECHARGE")
+                            cmd.cas.eq(1)
                         )
+                    ).Else(
+                        NextState("PRECHARGE")
                     )
                 ).Else(
                     If(activate_allowed,
@@ -162,13 +146,6 @@ class BankMachine(Module):
                 )
             )
         )
-        fsm.act("AUTOPRECHARGE",
-            If(self.precharge_timer.done,
-                cmd.valid.eq(0),
-                NextState("TRP")
-            ),
-            track_close.eq(1)
-        )
         fsm.act("PRECHARGE",
             # Note: we are presenting the column address, A10 is always low
             If(self.precharge_timer.done,