From f57dfad6a4673e0733d7e53ebb0d8deb2287e3b5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 15 Dec 2016 19:07:43 +0100 Subject: [PATCH] frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter --- litedram/common.py | 2 ++ litedram/frontend/adaptation.py | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/litedram/common.py b/litedram/common.py index 89a59a0..40d88c3 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -101,6 +101,8 @@ class LiteDRAMPort: self.wdata = stream.Endpoint(wdata_description(dw)) self.rdata = stream.Endpoint(rdata_description(dw)) + self.flush = Signal() + class LiteDRAMWritePort(LiteDRAMPort): def __init__(self, *args, **kwargs): diff --git a/litedram/frontend/adaptation.py b/litedram/frontend/adaptation.py index e76697f..c7fbe94 100644 --- a/litedram/frontend/adaptation.py +++ b/litedram/frontend/adaptation.py @@ -267,7 +267,9 @@ class LiteDRAMReadPortUpConverter(Module): port_to.rdata.connect(rdata_buffer.sink), rdata_buffer.source.connect(rdata_converter.sink), rdata_chunk_valid.eq((cmd_buffer.source.sel & rdata_chunk) != 0), - If(cmd_buffer.source.valid, + If(port_from.flush, + rdata_converter.source.ready.eq(1) + ).Elif(cmd_buffer.source.valid, If(rdata_chunk_valid, port_from.rdata.valid.eq(rdata_converter.source.valid), port_from.rdata.data.eq(rdata_converter.source.data),