From f8ac00a8ab0ce85c1bde71408551b3ace0e9f37e Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Wed, 15 Sep 2021 12:54:48 +0200 Subject: [PATCH] lpddr5: sim: add write leveling step as well Signed-off-by: Alessandro Comodi --- litedram/phy/lpddr5/simphy.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/litedram/phy/lpddr5/simphy.py b/litedram/phy/lpddr5/simphy.py index 0cf8589..a19f0e4 100644 --- a/litedram/phy/lpddr5/simphy.py +++ b/litedram/phy/lpddr5/simphy.py @@ -51,10 +51,20 @@ class LPDDR5SimPHY(SimSerDesMixin, LPDDR5PHY): # fake delays (make no nsense in simulation, but sdram.c expects them) self.settings.read_leveling = True - self.settings.delays = 1 self._rdly_dq_rst = CSR() self._rdly_dq_inc = CSR() + self.settings.write_leveling = True + self._cdly_rst = CSR() + self._cdly_inc = CSR() + self._wdly_dq_rst = CSR() + self._wdly_dq_inc = CSR() + self._wdly_dqs_rst = CSR() + self._wdly_dqs_inc = CSR() + self._half_sys8x_taps = CSR() + + self.settings.delays = 1 + delay = lambda sig, cycles: delayed(self, sig, cycles=cycles) ddr_ck = dict(clkdiv="sys", clk="sys2x") ddr_ca = dict(clkdiv="sys", clk="sys4x")