diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index 163a0fc..d7e47c5 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -19,8 +19,10 @@
 #define SDRAM_PHY_XDR 2
 #define SDRAM_PHY_DATABITS 64
 #define SDRAM_PHY_PHASES 4
+#define SDRAM_PHY_CL 7
+#define SDRAM_PHY_CWL 6
 #define SDRAM_PHY_CMD_LATENCY 1
-#define SDRAM_PHY_RDPHASE 1
+#define SDRAM_PHY_RDPHASE 0
 #define SDRAM_PHY_WRPHASE 1
 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
 #define SDRAM_PHY_READ_LEVELING_CAPABLE
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index d832509..4691ac3 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -19,8 +19,10 @@
 #define SDRAM_PHY_XDR 2
 #define SDRAM_PHY_DATABITS 64
 #define SDRAM_PHY_PHASES 4
+#define SDRAM_PHY_CL 9
+#define SDRAM_PHY_CWL 9
 #define SDRAM_PHY_CMD_LATENCY 1
-#define SDRAM_PHY_RDPHASE 3
+#define SDRAM_PHY_RDPHASE 2
 #define SDRAM_PHY_WRPHASE 2
 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
 #define SDRAM_PHY_WRITE_LEVELING_REINIT
diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h
index 5d1178c..69bc521 100644
--- a/test/reference/sdr_init.h
+++ b/test/reference/sdr_init.h
@@ -19,6 +19,8 @@
 #define SDRAM_PHY_XDR 1
 #define SDRAM_PHY_DATABITS 16
 #define SDRAM_PHY_PHASES 1
+#define SDRAM_PHY_CL 2
+#define SDRAM_PHY_CWL 2
 #define SDRAM_PHY_RDPHASE 0
 #define SDRAM_PHY_WRPHASE 0