From f9d00f137b9f969dc55e2389bb4fa69c3b316466 Mon Sep 17 00:00:00 2001
From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Tue, 28 Jan 2020 12:38:17 +0100
Subject: [PATCH] phy/model: simulate write latency

---
 litedram/phy/model.py | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/litedram/phy/model.py b/litedram/phy/model.py
index 2125fd3..0d5831a 100644
--- a/litedram/phy/model.py
+++ b/litedram/phy/model.py
@@ -196,13 +196,15 @@ class SDRAMPHYModel(Module):
             self.comb += Case(precharges, cases)
 
             # Bank writes
+            bank_write = Signal()
+            bank_write_col = Signal(max=ncols)
             writes = Signal(len(phases))
             cases  = {}
             for np, phase in enumerate(phases):
                 self.comb += writes[np].eq(phase.write)
                 cases[2**np] = [
-                    bank.write.eq(phase.bank == nb),
-                    bank.write_col.eq(phase.address)
+                    bank_write.eq(phase.bank == nb),
+                    bank_write_col.eq(phase.address)
                 ]
             self.comb += Case(writes, cases)
             self.comb += [
@@ -210,6 +212,22 @@ class SDRAMPHYModel(Module):
                 bank.write_mask.eq(Cat(*[phase.wrdata_mask for phase in phases]))
             ]
 
+            # Simulate write latency
+            for i in range(self.settings.write_latency):
+                new_bank_write     = Signal()
+                new_bank_write_col = Signal(max=ncols)
+                self.sync += [
+                    new_bank_write.eq(bank_write),
+                    new_bank_write_col.eq(bank_write_col)
+                ]
+                bank_write = new_bank_write
+                bank_write_col = new_bank_write_col
+
+            self.comb += [
+                bank.write.eq(bank_write),
+                bank.write_col.eq(bank_write_col)
+            ]
+
             # Bank reads
             reads = Signal(len(phases))
             cases = {}