From fa0f3b27778639caa4c473309500956bdc83e3d6 Mon Sep 17 00:00:00 2001
From: John Sully <john@LAPTOP-VGQL9KOL.CSQUARE.local>
Date: Sat, 22 Sep 2018 17:15:19 +0200
Subject: [PATCH] Use the ready signal for cas_allowed so that arbitrators know
 not to iterate

---
 litedram/core/bankmachine.py | 27 ++++++++++++---------------
 litedram/core/multiplexer.py |  3 +--
 2 files changed, 13 insertions(+), 17 deletions(-)

diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py
index 1df3aa6..d03c8df 100644
--- a/litedram/core/bankmachine.py
+++ b/litedram/core/bankmachine.py
@@ -32,7 +32,6 @@ class BankMachine(Module):
         self.refresh_req = Signal()
         self.refresh_gnt = Signal()
         self.ras_allowed = ras_allowed = Signal()
-        self.cas_allowed = cas_allowed = Signal()
         a = settings.geom.addressbits
         ba = settings.geom.bankbits + log2_int(nranks)
         self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(a, ba))
@@ -108,20 +107,18 @@ class BankMachine(Module):
             ).Elif(cmd_buffer.source.valid,
                 If(has_openrow,
                     If(hit,
-                        If(cas_allowed,
-                            cmd.valid.eq(1),
-                            If(cmd_buffer.source.we,
-                                req.wdata_ready.eq(cmd.ready),
-                                cmd.is_write.eq(1),
-                                cmd.we.eq(1),
-                            ).Else(
-                                req.rdata_valid.eq(cmd.ready),
-                                cmd.is_read.eq(1)
-                            ),
-                            cmd.cas.eq(1),
-                            If(cmd.ready & auto_precharge,
-                               NextState("AUTOPRECHARGE")
-                            )
+                        cmd.valid.eq(1),
+                        If(cmd_buffer.source.we,
+                            req.wdata_ready.eq(cmd.ready),
+                            cmd.is_write.eq(1),
+                            cmd.we.eq(1),
+                        ).Else(
+                            req.rdata_valid.eq(cmd.ready),
+                            cmd.is_read.eq(1)
+                        ),
+                        cmd.cas.eq(1),
+                        If(cmd.ready & auto_precharge,
+                           NextState("AUTOPRECHARGE")
                         )
                     ).Else(
                         NextState("PRECHARGE")
diff --git a/litedram/core/multiplexer.py b/litedram/core/multiplexer.py
index 2e8eb68..541e464 100644
--- a/litedram/core/multiplexer.py
+++ b/litedram/core/multiplexer.py
@@ -226,7 +226,6 @@ class Multiplexer(Module, AutoCSR):
 
         # CAS control
         self.comb += cas_allowed.eq(tccdcon.ready)
-        self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines]
 
         # tWTR timing (Write to Read delay)
         self.submodules.twtrcon = twtrcon = tXXDController(
@@ -306,7 +305,7 @@ class Multiplexer(Module, AutoCSR):
             choose_req.want_reads.eq(1),
             choose_cmd.want_activates.eq(ras_allowed),
             choose_cmd.cmd.ready.eq(~choose_cmd.activate() | ras_allowed),
-            choose_req.cmd.ready.eq(1),
+            choose_req.cmd.ready.eq(cas_allowed),
             steerer_sel(steerer, "read"),
             If(write_available,
                 # TODO: switch only after several cycles of ~read_available?