From fbd7ae3e627718664460f2d2726b2e2d7fe73c11 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 May 2019 10:02:02 +0200
Subject: [PATCH] modules: make IS43TR16128B consistent with others
 SDRAMModules

---
 litedram/modules.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/litedram/modules.py b/litedram/modules.py
index 0c128c3..af24701 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -310,7 +310,7 @@ class K4B2G1646F(SDRAMModule):
     speedgrade_timings["default"] = speedgrade_timings["1600"]
 
 
-class IS43TR16128B_125K(SDRAMModule):
+class IS43TR16128B(SDRAMModule):
     memtype = "DDR3"
     # geometry
     nbanks = 8
@@ -319,8 +319,9 @@ class IS43TR16128B_125K(SDRAMModule):
     # timings
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6))
     speedgrade_timings = {
-        "default": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=160, tFAW=(None, 40), tRAS=35),
+        "1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=160, tFAW=(None, 40), tRAS=35),
     }
+    speedgrade_timings["default"] = speedgrade_timings["1600"]
 
 
 # DDR3 (SO-DIMM)