From fc4175108092db7afb5bf6a874a57bdede8d803a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 Jul 2019 11:30:57 +0200 Subject: [PATCH] frontend/dma: simplify rsv_level expose --- litedram/frontend/dma.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py index 3e6ac0a..b7c773c 100644 --- a/litedram/frontend/dma.py +++ b/litedram/frontend/dma.py @@ -77,15 +77,15 @@ class LiteDRAMDMAReader(Module): # incremented when data is planned to be queued # decremented when data is dequeued data_dequeued = Signal() - self.rsv_level = Signal(max=fifo_depth+1) + self.rsv_level = rsv_level = Signal(max=fifo_depth+1) self.sync += [ If(request_issued, - If(~data_dequeued, self.rsv_level.eq(self.rsv_level + 1)) + If(~data_dequeued, rsv_level.eq(self.rsv_level + 1)) ).Elif(data_dequeued, - self.rsv_level.eq(self.rsv_level - 1) + rsv_level.eq(rsv_level - 1) ) ] - self.comb += request_enable.eq(self.rsv_level != fifo_depth) + self.comb += request_enable.eq(rsv_level != fifo_depth) # FIFO fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered)