diff --git a/test/phy_common.py b/test/phy_common.py
index e5af262..13bfed8 100644
--- a/test/phy_common.py
+++ b/test/phy_common.py
@@ -12,11 +12,11 @@ from typing import Mapping, Sequence
 
 from migen import *
 
+from litex.gen.sim.core import run_simulation as _run_simulation
+
 from litedram.phy import dfi
 from litedram.phy.utils import chunks
 
-from test.test_phy_utils import run_simulation as _run_simulation
-
 BOLD = '\033[1m'
 HIGHLIGHT = '\033[91m'
 CLEAR = '\033[0m'
diff --git a/test/test_lpddr4.py b/test/test_lpddr4.py
index 1d2c3a2..ba8a6b4 100644
--- a/test/test_lpddr4.py
+++ b/test/test_lpddr4.py
@@ -7,8 +7,9 @@
 import re
 import copy
 import unittest
-from collections import defaultdict
 from typing import Mapping
+from functools import partial
+from collections import defaultdict
 
 from migen import *
 
@@ -16,7 +17,8 @@ from litedram.phy.utils import bit
 from litedram.phy.lpddr4.simphy import LPDDR4SimPHY, DoubleRateLPDDR4SimPHY
 from litedram.phy.lpddr4 import simsoc
 
-from test.phy_common import DFISequencer, PadChecker, run_simulation as _run_simulation
+import test.phy_common
+from test.phy_common import DFISequencer, PadChecker
 
 
 # Migen simulator supports reset signals so we could add CRG to start all the signals
@@ -38,18 +40,14 @@ from test.phy_common import DFISequencer, PadChecker, run_simulation as _run_sim
 # sys8x_90_ddr does not trigger at the simulation start (not an edge),
 # BUT a generator starts before first edge, so a `yield` is needed to wait until the first
 # rising edge!
-CLOCKS = {
+run_simulation = partial(test.phy_common.run_simulation, clocks={
     "sys":          (64, 31),
     "sys2x":        (32, 15),
     "sys8x":        ( 8,  3),
     "sys8x_ddr":    ( 4,  1),
     "sys8x_90":     ( 8,  1),
     "sys8x_90_ddr": ( 4,  3),
-}
-
-def run_simulation(dut, generators, **kwargs):
-    _run_simulation(dut, generators, CLOCKS, **kwargs)
-
+})
 
 
 def dfi_data_to_dq(dq_i, dfi_phases, dfi_name, nphases=8):
diff --git a/test/test_phy_utils.py b/test/test_phy_utils.py
index 453c912..5f310f0 100644
--- a/test/test_phy_utils.py
+++ b/test/test_phy_utils.py
@@ -6,27 +6,27 @@
 
 import unittest
 import itertools
+from functools import partial
 
 from migen import *
 
 from litedram.phy.utils import Serializer, Deserializer, Latency, chunks, bit, ConstBitSlip
 
-from test.phy_common import run_simulation
+import test.phy_common
+
+
+run_serializers_simulation = partial(test.phy_common.run_simulation, clocks={
+    "sys":          (64, 31),
+    "sys_11_25":    (64, 29),  # aligned to sys8x_90 (phase shift of 11.25)
+    "sys2x":        (32, 15),
+    "sys8x":        ( 8,  3),
+    "sys8x_ddr":    ( 4,  1),
+    "sys8x_90":     ( 8,  1),
+    "sys8x_90_ddr": ( 4,  3),
+})
 
 
 class TestSimSerializers(unittest.TestCase):
-    def run_simulation(self, dut, generators, **kwargs):
-        clocks = {
-            "sys":          (64, 31),
-            "sys_11_25":    (64, 29),  # aligned to sys8x_90 (phase shift of 11.25)
-            "sys2x":        (32, 15),
-            "sys8x":        ( 8,  3),
-            "sys8x_ddr":    ( 4,  1),
-            "sys8x_90":     ( 8,  1),
-            "sys8x_90_ddr": ( 4,  3),
-        }
-        run_simulation(dut, generators, clocks, **kwargs)
-
     @staticmethod
     def data_generator(i, datas):
         for data in datas:
@@ -56,7 +56,7 @@ class TestSimSerializers(unittest.TestCase):
             clkgen: self.data_generator(dut.i, datas),
             clkcheck: self.data_checker(dut.o, received, n=len(datas) * data_width, latency=latency * data_width, yield1=True),
         }
-        self.run_simulation(dut, generators, **kwargs)
+        run_serializers_simulation(dut, generators, **kwargs)
 
         received = list(chunks(received, data_width))
         datas  = [[bit(i, d) for i in range(data_width)] for d in datas]
@@ -75,7 +75,7 @@ class TestSimSerializers(unittest.TestCase):
             clkcheck: self.data_checker(dut.o, received, n=len(datas), latency=latency),
         }
 
-        self.run_simulation(dut, generators, **kwargs)
+        run_serializers_simulation(dut, generators, **kwargs)
 
         received = [[bit(i, d) for i in range(data_width)] for d in received]
         self.assertEqual(received, datas)