From 98f2f24e2025e627731675ea2ecc2feb3737f463 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Fri, 16 Apr 2021 15:12:44 +0200 Subject: [PATCH 1/2] init: enable DQ-DQS training for LPDDR4 PHYs with output delays --- litedram/init.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litedram/init.py b/litedram/init.py index 5d8d53d..4b684c5 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -690,6 +690,8 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): 'K7LPDDR4PHY', 'V7LPDDR4PHY']: r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n" r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" + if phytype in ['K7LPDDR4PHY', 'V7LPDDR4PHY']: + r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n" if phytype in ["ECP5DDRPHY"]: r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" if phytype in ["LPDDR4SIMPHY"]: From ebaf63479d42b8862ebbbe3b42736c233d0d0670 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Fri, 16 Apr 2021 15:35:35 +0200 Subject: [PATCH 2/2] init/lpddr4: modify pull-down drive strength to improve signal quality --- litedram/init.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litedram/init.py b/litedram/init.py index 4b684c5..dde56a3 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -456,6 +456,7 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings): bl = 16 dq_odt = "RZQ/2" ca_odt = "RZQ/2" + pull_down_drive_strength = "RZQ/3" def get_nwr(): frequency_ranges = [ # Table 28. Frequency Ranges for RL, WL, nWR, and nRTP Settings @@ -575,7 +576,7 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings): (0, 1, 1), (1, 1, 0), (2, 1, 0), - (3, 3, odt_map["RZQ/6"]), + (3, 3, odt_map[pull_down_drive_strength]), (6, 1, 0), (7, 1, 0), ])