From fe1bb083efb64d1b7f2e54be8df0d84d634b979a Mon Sep 17 00:00:00 2001
From: Anton Blanchard <anton@ozlabs.org>
Date: Mon, 9 Aug 2021 10:35:17 +1000
Subject: [PATCH] litedram_gen: Fix error with --sim option

It looks like commit 317072a1982d ("litedram_gen: Add initial SDRAM
support (with ULX3S example)") broke building with the --sim option.
---
 litedram/gen.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litedram/gen.py b/litedram/gen.py
index 59a8ccc..1064b3d 100755
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -501,7 +501,7 @@ class LiteDRAMCore(SoCCore):
                 memtype    = sdram_module.memtype,
                 data_width = core_config["sdram_module_nb"]*8,
                 clk_freq   = sdram_clk_freq)
-            self.submodules.ddrphy = SDRAMPHYModel(
+            self.submodules.ddrphy = sdram_phy = SDRAMPHYModel(
                 module    = sdram_module,
                 settings  = phy_settings,
                 clk_freq  = sdram_clk_freq)