From fe1e7a306fdb4da04d4f091bb2812865917be1b4 Mon Sep 17 00:00:00 2001 From: "Deployment Bot (from Travis CI)" Date: Tue, 17 Nov 2020 16:53:00 +0000 Subject: [PATCH] Deploy enjoy-digital/litedram to github.com/enjoy-digital/litedram.git:gh-pages --- cache.json | 2 +- index.html | 42 +++++++++++++++++++++--------------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/cache.json b/cache.json index a6eed61..0694794 100644 --- a/cache.json +++ b/cache.json @@ -1 +1 @@ -[{"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_0"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\n CC umodsi3.o\\n CC udivsi3.o\\n CC divsi3.o\\n CC modsi3.o\\n CC comparesf2.o\\n CC comparedf2.o\\n CC negsf2.o\\n CC negdf2.o\\n CC addsf3.o\\n CC subsf3.o\\n CC mulsf3.o\\n CC divsf3.o\\n CC lshrdi3.o\\n CC muldi3.o\\n CC divdi3.o\\n CC ashldi3.o\\n CC ashrdi3.o\\n CC udivmoddi4.o\\n CC floatsisf.o\\n CC floatunsisf.o\\n CC fixsfsi.o\\n CC fixdfdi.o\\n CC fixunssfsi.o\\n CC fixunsdfdi.o\\n CC adddf3.o\\n CC subdf3.o\\n CC muldf3.o\\n CC divdf3.o\\n CC floatsidf.o\\n CC floatunsidf.o\\n CC floatdidf.o\\n CC fixdfsi.o\\n CC fixunsdfsi.o\\n CC clzsi2.o\\n CC ctzsi2.o\\n CC udivdi3.o\\n CC umoddi3.o\\n CC moddi3.o\\n CC ucmpdi2.o\\n CC mulsi3.o\\n AR libcompiler_rt.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC crt0.o\\n CC exception.o\\n CC libc.o\\n CC errno.o\\n CC crc16.o\\n CC crc32.o\\n CC console.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC qsort.o\\n CC strtod.o\\n CC spiflash.o\\n CC strcasecmp.o\\n CC i2c.o\\n CC div64.o\\n CC progress.o\\n CC memtest.o\\n CC sim_debug.o\\n CC vsnprintf.o\\n AR libbase.a\\n CC vsnprintf-nofloat.o\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC tftp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\n CC ffunicode.o\\n CC ff.o\\n AR libfatfs.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot-helper.o\\n CC boot.o\\n CC helpers.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n CC complete.o\\n CC readline.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/../.. -o xgmii_ethernet.o /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,xgmii_ethernet.so -o xgmii_ethernet.so xgmii_ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/ethernet/../.. -o ethernet.o /home/travis/litex/litex/build/sim/core/modules/ethernet/ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,ethernet.so -o ethernet.so ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2console/../.. -o serial2console.o /home/travis/litex/litex/build/sim/core/modules/serial2console/serial2console.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2console.so -o serial2console.so serial2console.o\\nrm serial2console.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2tcp/../.. -o serial2tcp.o /home/travis/litex/litex/build/sim/core/modules/serial2tcp/serial2tcp.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2tcp.so -o serial2tcp.so serial2tcp.o\\nrm serial2tcp.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/clocker/../.. -o clocker.o /home/travis/litex/litex/build/sim/core/modules/clocker/clocker.c\\ncc -levent -shared -fPIC -Wl,-soname,clocker.so -o clocker.so clocker.o\\nrm clocker.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/spdeeprom/../.. -o spdeeprom.o /home/travis/litex/litex/build/sim/core/modules/spdeeprom/spdeeprom.c\\ncc -levent -shared -fPIC -Wl,-soname,spdeeprom.so -o spdeeprom.so spdeeprom.o\\nrm spdeeprom.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55cb7fed8130)\\n[serial2console] loaded (0x55cb7fed8130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55cb7fed8130)\\n[serial2tcp] loaded (0x55cb7fed8130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:38:03\\n\\r BIOS CRC passed (8310a3c3)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000034\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_1"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\n CC umodsi3.o\\n CC udivsi3.o\\n CC divsi3.o\\n CC modsi3.o\\n CC comparesf2.o\\n CC comparedf2.o\\n CC negsf2.o\\n CC negdf2.o\\n CC addsf3.o\\n CC subsf3.o\\n CC mulsf3.o\\n CC divsf3.o\\n CC lshrdi3.o\\n CC muldi3.o\\n CC divdi3.o\\n CC ashldi3.o\\n CC ashrdi3.o\\n CC udivmoddi4.o\\n CC floatsisf.o\\n CC floatunsisf.o\\n CC fixsfsi.o\\n CC fixdfdi.o\\n CC fixunssfsi.o\\n CC fixunsdfdi.o\\n CC adddf3.o\\n CC subdf3.o\\n CC muldf3.o\\n CC divdf3.o\\n CC floatsidf.o\\n CC floatunsidf.o\\n CC floatdidf.o\\n CC fixdfsi.o\\n CC fixunsdfsi.o\\n CC clzsi2.o\\n CC ctzsi2.o\\n CC udivdi3.o\\n CC umoddi3.o\\n CC moddi3.o\\n CC ucmpdi2.o\\n CC mulsi3.o\\n AR libcompiler_rt.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC crt0.o\\n CC exception.o\\n CC libc.o\\n CC errno.o\\n CC crc16.o\\n CC crc32.o\\n CC console.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC qsort.o\\n CC strtod.o\\n CC spiflash.o\\n CC strcasecmp.o\\n CC i2c.o\\n CC div64.o\\n CC progress.o\\n CC memtest.o\\n CC sim_debug.o\\n CC vsnprintf.o\\n AR libbase.a\\n CC vsnprintf-nofloat.o\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC tftp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\n CC ffunicode.o\\n CC ff.o\\n AR libfatfs.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot-helper.o\\n CC boot.o\\n CC helpers.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n CC complete.o\\n CC readline.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/../.. -o xgmii_ethernet.o /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,xgmii_ethernet.so -o xgmii_ethernet.so xgmii_ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/ethernet/../.. -o ethernet.o /home/travis/litex/litex/build/sim/core/modules/ethernet/ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,ethernet.so -o ethernet.so ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2console/../.. -o serial2console.o /home/travis/litex/litex/build/sim/core/modules/serial2console/serial2console.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2console.so -o serial2console.so serial2console.o\\nrm serial2console.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2tcp/../.. -o serial2tcp.o /home/travis/litex/litex/build/sim/core/modules/serial2tcp/serial2tcp.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2tcp.so -o serial2tcp.so serial2tcp.o\\nrm serial2tcp.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/clocker/../.. -o clocker.o /home/travis/litex/litex/build/sim/core/modules/clocker/clocker.c\\ncc -levent -shared -fPIC -Wl,-soname,clocker.so -o clocker.so clocker.o\\nrm clocker.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/spdeeprom/../.. -o spdeeprom.o /home/travis/litex/litex/build/sim/core/modules/spdeeprom/spdeeprom.c\\ncc -levent -shared -fPIC -Wl,-soname,spdeeprom.so -o spdeeprom.so spdeeprom.o\\nrm spdeeprom.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x560bdae17130)\\n[serial2console] loaded (0x560bdae17130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x560bdae17130)\\n[serial2tcp] loaded (0x560bdae17130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:38:03\\n\\r BIOS CRC passed (8310a3c3)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000034\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_2"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5567932ad130)\\n[serial2console] loaded (0x5567932ad130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5567932ad130)\\n[serial2tcp] loaded (0x5567932ad130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:38:43\\n\\r BIOS CRC passed (eb7bec1e)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000084\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000762\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_3"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55fab4764130)\\n[serial2console] loaded (0x55fab4764130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55fab4764130)\\n[serial2tcp] loaded (0x55fab4764130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:38:43\\n\\r BIOS CRC passed (eb7bec1e)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000188\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000633\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_4"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55c07fe20130)\\n[serial2console] loaded (0x55c07fe20130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55c07fe20130)\\n[serial2tcp] loaded (0x55c07fe20130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:39:21\\n\\r BIOS CRC passed (355ef62a)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000042\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_5"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bb12446130)\\n[serial2console] loaded (0x55bb12446130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bb12446130)\\n[serial2tcp] loaded (0x55bb12446130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:39:21\\n\\r BIOS CRC passed (355ef62a)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000136\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_6"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x558b31950130)\\n[serial2console] loaded (0x558b31950130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x558b31950130)\\n[serial2tcp] loaded (0x558b31950130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:40:03\\n\\r BIOS CRC passed (5062019f)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000074\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001060\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_7"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x559c4ae40130)\\n[serial2console] loaded (0x559c4ae40130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x559c4ae40130)\\n[serial2tcp] loaded (0x559c4ae40130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:40:03\\n\\r BIOS CRC passed (5062019f)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000126\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000923\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_8"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55719e841130)\\n[serial2console] loaded (0x55719e841130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55719e841130)\\n[serial2tcp] loaded (0x55719e841130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:40:44\\n\\r BIOS CRC passed (158cf32d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000042\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_9"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564b9d656130)\\n[serial2console] loaded (0x564b9d656130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564b9d656130)\\n[serial2tcp] loaded (0x564b9d656130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:40:44\\n\\r BIOS CRC passed (158cf32d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000042\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_10"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5633fd0e0130)\\n[serial2console] loaded (0x5633fd0e0130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5633fd0e0130)\\n[serial2tcp] loaded (0x5633fd0e0130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:41:25\\n\\r BIOS CRC passed (50d071a4)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000878\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001020\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_11"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55c486a6d130)\\n[serial2console] loaded (0x55c486a6d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55c486a6d130)\\n[serial2tcp] loaded (0x55c486a6d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:41:26\\n\\r BIOS CRC passed (cba9e919)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000706\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000900\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_12"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e136fc4130)\\n[serial2console] loaded (0x55e136fc4130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e136fc4130)\\n[serial2tcp] loaded (0x55e136fc4130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:42:07\\n\\r BIOS CRC passed (8fe4e3d1)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000050\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_13"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55866ca24130)\\n[serial2console] loaded (0x55866ca24130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55866ca24130)\\n[serial2tcp] loaded (0x55866ca24130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:42:07\\n\\r BIOS CRC passed (8fe4e3d1)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000144\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_14"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x560d47847130)\\n[serial2console] loaded (0x560d47847130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x560d47847130)\\n[serial2tcp] loaded (0x560d47847130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:42:52\\n\\r BIOS CRC passed (fdb291ed)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000728\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001188\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_15"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55ed71876130)\\n[serial2console] loaded (0x55ed71876130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55ed71876130)\\n[serial2tcp] loaded (0x55ed71876130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:42:53\\n\\r BIOS CRC passed (3db51bb9)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000695\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001189\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_16"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2646: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2670: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2687: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2715: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2821: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2838: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2972: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2989: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3123: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3168: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3250: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3319: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3336: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3401: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3425: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3442: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3470: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3487: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3511: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3528: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3552: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3576: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3621: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3638: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3662: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3679: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3703: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3727: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3744: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14981: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15012: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15043: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15074: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15105: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15136: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15167: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15198: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15394: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15436: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55dac42d8130)\\n[serial2console] loaded (0x55dac42d8130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55dac42d8130)\\n[serial2tcp] loaded (0x55dac42d8130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:43:37\\n\\r BIOS CRC passed (0e1236b6)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000030\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:13452: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_17"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2646: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2670: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2687: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2715: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2821: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2838: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2972: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2989: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3123: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3168: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3250: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3319: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3336: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3401: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3425: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3442: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3470: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3487: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3511: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3528: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3552: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3576: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3621: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3638: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3662: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3679: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3703: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3727: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3744: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14981: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15012: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15043: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15074: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15105: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15136: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15167: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15198: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15394: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15436: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x561d628f1130)\\n[serial2console] loaded (0x561d628f1130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x561d628f1130)\\n[serial2tcp] loaded (0x561d628f1130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:43:37\\n\\r BIOS CRC passed (0e1236b6)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000041\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000053\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13452: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_18"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3175: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3326: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3367: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3408: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3436: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3453: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3477: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3494: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3542: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3587: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3604: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3628: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3693: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3710: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3844: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3889: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3906: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3995: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4040: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4057: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16209: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16298: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16387: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16476: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16565: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16654: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16743: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16832: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17214: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17256: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564d1e657130)\\n[serial2console] loaded (0x564d1e657130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564d1e657130)\\n[serial2tcp] loaded (0x564d1e657130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:44:16\\n\\r BIOS CRC passed (98aab346)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000132\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_19"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3175: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3326: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3367: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3408: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3436: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3453: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3477: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3494: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3542: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3587: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3604: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3628: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3693: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3710: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3844: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3889: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3906: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3995: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4040: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4057: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16209: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16298: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16387: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16476: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16565: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16654: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16743: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16832: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17214: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17256: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x557d65ab1130)\\n[serial2console] loaded (0x557d65ab1130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x557d65ab1130)\\n[serial2tcp] loaded (0x557d65ab1130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:44:16\\n\\r BIOS CRC passed (98aab346)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000041\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000157\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_20"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2860: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2901: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2929: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2946: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3121: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3138: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3186: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3203: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3231: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3272: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3289: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3313: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3354: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3382: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3399: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3423: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3440: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3464: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3488: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3533: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3550: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3574: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3591: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3615: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3639: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3656: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3701: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3742: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3790: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3807: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3852: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3876: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3893: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15977: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16066: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16155: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16244: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16333: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16422: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16511: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16600: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16944: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16986: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5601e5bd6130)\\n[serial2console] loaded (0x5601e5bd6130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5601e5bd6130)\\n[serial2tcp] loaded (0x5601e5bd6130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:44:58\\n\\r BIOS CRC passed (abca8645)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000017\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14426: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_21"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2860: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2901: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2929: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2946: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3121: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3138: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3186: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3203: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3231: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3272: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3289: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3313: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3354: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3382: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3399: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3423: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3440: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3464: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3488: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3533: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3550: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3574: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3591: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3615: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3639: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3656: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3701: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3742: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3790: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3807: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3852: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3876: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3893: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15977: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16066: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16155: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16244: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16333: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16422: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16511: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16600: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16944: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16986: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56181a5c7130)\\n[serial2console] loaded (0x56181a5c7130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56181a5c7130)\\n[serial2tcp] loaded (0x56181a5c7130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:44:58\\n\\r BIOS CRC passed (abca8645)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000117\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000048\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14426: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_22"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3169: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3197: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3214: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3348: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3365: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3389: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3454: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3471: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3499: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3540: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3557: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3581: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3650: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3801: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3859: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4010: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4161: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17205: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17384: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17563: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17742: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17921: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18100: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18279: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18458: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19020: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19062: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x555d05207130)\\n[serial2console] loaded (0x555d05207130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x555d05207130)\\n[serial2tcp] loaded (0x555d05207130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:45:40\\n\\r BIOS CRC passed (45383a09)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000119\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15632: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_23"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3169: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3197: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3214: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3348: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3365: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3389: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3454: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3471: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3499: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3540: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3557: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3581: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3650: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3801: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3859: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4010: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4161: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17205: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17384: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17563: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17742: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17921: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18100: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18279: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18458: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19020: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19062: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d9fc8aa130)\\n[serial2console] loaded (0x55d9fc8aa130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d9fc8aa130)\\n[serial2tcp] loaded (0x55d9fc8aa130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:45:40\\n\\r BIOS CRC passed (45383a09)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000117\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000152\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15632: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_24"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d39ce92130)\\n[serial2console] loaded (0x55d39ce92130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d39ce92130)\\n[serial2tcp] loaded (0x55d39ce92130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:46:25\\n\\r BIOS CRC passed (20c83557)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000027\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_25"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a59a4b9130)\\n[serial2console] loaded (0x55a59a4b9130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a59a4b9130)\\n[serial2tcp] loaded (0x55a59a4b9130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:46:25\\n\\r BIOS CRC passed (20c83557)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000027\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_26"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x562f1981e130)\\n[serial2console] loaded (0x562f1981e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x562f1981e130)\\n[serial2tcp] loaded (0x562f1981e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:46:47\\n\\r BIOS CRC passed (005c5e37)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000204\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001199\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_27"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d98aa3e130)\\n[serial2console] loaded (0x55d98aa3e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d98aa3e130)\\n[serial2tcp] loaded (0x55d98aa3e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:46:47\\n\\r BIOS CRC passed (005c5e37)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000380\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001005\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_28"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x558517577130)\\n[serial2console] loaded (0x558517577130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x558517577130)\\n[serial2tcp] loaded (0x558517577130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:47:10\\n\\r BIOS CRC passed (25f97afa)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000035\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_29"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x559f9763d130)\\n[serial2console] loaded (0x559f9763d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x559f9763d130)\\n[serial2tcp] loaded (0x559f9763d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:47:10\\n\\r BIOS CRC passed (25f97afa)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000129\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_30"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d7e6066130)\\n[serial2console] loaded (0x55d7e6066130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d7e6066130)\\n[serial2tcp] loaded (0x55d7e6066130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:47:34\\n\\r BIOS CRC passed (6b22ad1d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000166\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001801\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_31"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b67776c130)\\n[serial2console] loaded (0x55b67776c130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b67776c130)\\n[serial2tcp] loaded (0x55b67776c130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:47:34\\n\\r BIOS CRC passed (6b22ad1d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000269\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001550\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_32"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bb033b3130)\\n[serial2console] loaded (0x55bb033b3130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bb033b3130)\\n[serial2tcp] loaded (0x55bb033b3130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:47:57\\n\\r BIOS CRC passed (f03a2aa7)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000035\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_33"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x555cabe0e130)\\n[serial2console] loaded (0x555cabe0e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x555cabe0e130)\\n[serial2tcp] loaded (0x555cabe0e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:47:57\\n\\r BIOS CRC passed (f03a2aa7)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000035\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_34"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d7daec9130)\\n[serial2console] loaded (0x55d7daec9130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d7daec9130)\\n[serial2tcp] loaded (0x55d7daec9130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:48:21\\n\\r BIOS CRC passed (0eaa01fc)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00001462\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001729\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_35"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5586a5b9a130)\\n[serial2console] loaded (0x5586a5b9a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5586a5b9a130)\\n[serial2tcp] loaded (0x5586a5b9a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:48:21\\n\\r BIOS CRC passed (0eaa01fc)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00001217\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001528\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_36"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56119c3c3130)\\n[serial2console] loaded (0x56119c3c3130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56119c3c3130)\\n[serial2tcp] loaded (0x56119c3c3130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:48:45\\n\\r BIOS CRC passed (01f60cc2)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000043\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_37"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55c97f231130)\\n[serial2console] loaded (0x55c97f231130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55c97f231130)\\n[serial2tcp] loaded (0x55c97f231130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:48:45\\n\\r BIOS CRC passed (01f60cc2)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000148\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_38"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bf9239a130)\\n[serial2console] loaded (0x55bf9239a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bf9239a130)\\n[serial2tcp] loaded (0x55bf9239a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:49:11\\n\\r BIOS CRC passed (33b71b20)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--=BIST-GENERATOR ticks: 00001371\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002276\\n============= \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_39"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b21135a130)\\n[serial2console] loaded (0x55b21135a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b21135a130)\\n[serial2tcp] loaded (0x55b21135a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:49:11\\n\\r BIOS CRC passed (33b71b20)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r-BIST-GENERATOR ticks: 00001113\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002067\\n-============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_40"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1782: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1809: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1829: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1867: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1899: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1910: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1957: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8271: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8302: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8333: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8364: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8560: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8602: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55fe3c871130)\\n[serial2console] loaded (0x55fe3c871130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55fe3c871130)\\n[serial2tcp] loaded (0x55fe3c871130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:49:37\\n\\r BIOS CRC passed (d1041332)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000023\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7676: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_41"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1782: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1809: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1829: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1867: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1899: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1910: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1957: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8271: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8302: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8333: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8364: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8560: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8602: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56500aeef130)\\n[serial2console] loaded (0x56500aeef130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56500aeef130)\\n[serial2tcp] loaded (0x56500aeef130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:49:37\\n\\r BIOS CRC passed (d1041332)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000069\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000082\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7676: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_42"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2061: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2092: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2220: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2321: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2353: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2395: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9403: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9492: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9581: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9670: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10052: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10094: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b7540e7130)\\n[serial2console] loaded (0x55b7540e7130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b7540e7130)\\n[serial2tcp] loaded (0x55b7540e7130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:49:59\\n\\r BIOS CRC passed (ae00b4ee)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000125\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8794: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_43"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2061: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2092: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2220: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2321: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2353: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2395: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9403: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9492: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9581: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9670: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10052: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10094: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55c9d042b130)\\n[serial2console] loaded (0x55c9d042b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55c9d042b130)\\n[serial2tcp] loaded (0x55c9d042b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:49:59\\n\\r BIOS CRC passed (ae00b4ee)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000069\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000250\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8794: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_44"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1964: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2027: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2139: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2155: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2267: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2341: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9171: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9260: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9349: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9438: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9782: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9824: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55ce2214d130)\\n[serial2console] loaded (0x55ce2214d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55ce2214d130)\\n[serial2tcp] loaded (0x55ce2214d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:50:24\\n\\r BIOS CRC passed (79ea91c1)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000014\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8562: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_45"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1964: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2027: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2139: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2155: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2267: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2341: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9171: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9260: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9349: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9438: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9782: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9824: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e21b823130)\\n[serial2console] loaded (0x55e21b823130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e21b823130)\\n[serial2tcp] loaded (0x55e21b823130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:50:24\\n\\r BIOS CRC passed (79ea91c1)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000209\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000077\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8562: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_46"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2205: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2232: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2306: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2380: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2407: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2418: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2434: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2481: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2492: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2519: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2535: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2551: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2562: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2582: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10303: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10482: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10661: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10840: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11402: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11444: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55aaa9cb7130)\\n[serial2console] loaded (0x55aaa9cb7130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55aaa9cb7130)\\n[serial2tcp] loaded (0x55aaa9cb7130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:50:47\\n\\r BIOS CRC passed (e2f2167b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000116\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9680: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_47"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2205: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2232: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2306: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2380: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2407: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2418: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2434: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2481: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2492: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2519: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2535: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2551: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2562: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2582: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10303: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10482: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10661: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10840: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11402: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11444: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x556b30c0a130)\\n[serial2console] loaded (0x556b30c0a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x556b30c0a130)\\n[serial2tcp] loaded (0x556b30c0a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:50:48\\n\\r BIOS CRC passed (aa86e9e8)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\nBIST-GENERATOR ticks: 00000209\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000245\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9680: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_48"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55558ddb4130)\\n[serial2console] loaded (0x55558ddb4130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55558ddb4130)\\n[serial2tcp] loaded (0x55558ddb4130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:51:13\\n\\r BIOS CRC passed (ad55d4f1)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000024\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_49"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5604f92d0130)\\n[serial2console] loaded (0x5604f92d0130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5604f92d0130)\\n[serial2tcp] loaded (0x5604f92d0130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:51:13\\n\\r BIOS CRC passed (ad55d4f1)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000024\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_50"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d931ead130)\\n[serial2console] loaded (0x55d931ead130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d931ead130)\\n[serial2tcp] loaded (0x55d931ead130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:51:33\\n\\r BIOS CRC passed (9cf556fd)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBootBIST-GENERATOR ticks: 00000852\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00004372\\n\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_51"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x561c1de5b130)\\n[serial2console] loaded (0x561c1de5b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x561c1de5b130)\\n[serial2tcp] loaded (0x561c1de5b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:51:34\\n\\r BIOS CRC passed (72970599)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1bBIST-GENERATOR ticks: 00001591\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00003673\\n[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_52"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d101cdf130)\\n[serial2console] loaded (0x55d101cdf130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d101cdf130)\\n[serial2tcp] loaded (0x55d101cdf130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:51:54\\n\\r BIOS CRC passed (2076838d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000033\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_53"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55f5b1ec8130)\\n[serial2console] loaded (0x55f5b1ec8130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55f5b1ec8130)\\n[serial2tcp] loaded (0x55f5b1ec8130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:51:54\\n\\r BIOS CRC passed (2076838d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000126\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_54"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564f025ee130)\\n[serial2console] loaded (0x564f025ee130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564f025ee130)\\n[serial2tcp] loaded (0x564f025ee130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:52:17\\n\\r BIOS CRC passed (12bf471c)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--BIST-GENERATOR ticks: 00000682\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00006803\\n\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_55"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e6705f2130)\\n[serial2console] loaded (0x55e6705f2130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e6705f2130)\\n[serial2tcp] loaded (0x55e6705f2130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:52:17\\n\\r BIOS CRC passed (12bf471c)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==========BIST-GENERATOR ticks: 00001051\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005803\\n========--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_56"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564f1a303130)\\n[serial2console] loaded (0x564f1a303130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564f1a303130)\\n[serial2tcp] loaded (0x564f1a303130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:52:40\\n\\r BIOS CRC passed (874c5166)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000032\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_57"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x555bdf967130)\\n[serial2console] loaded (0x555bdf967130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x555bdf967130)\\n[serial2tcp] loaded (0x555bdf967130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:52:40\\n\\r BIOS CRC passed (874c5166)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000032\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_58"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x555a0905b130)\\n[serial2console] loaded (0x555a0905b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x555a0905b130)\\n[serial2tcp] loaded (0x555a0905b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:53:02\\n\\r BIOS CRC passed (7d807880)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ================BIST-GENERATOR ticks: 00005414\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00006448\\n==--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_59"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5592dbe2a130)\\n[serial2console] loaded (0x5592dbe2a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5592dbe2a130)\\n[serial2tcp] loaded (0x5592dbe2a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:53:02\\n\\r BIOS CRC passed (7d807880)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m =========BIST-GENERATOR ticks: 00004705\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005779\\n=========--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_60"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55c969a88130)\\n[serial2console] loaded (0x55c969a88130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55c969a88130)\\n[serial2tcp] loaded (0x55c969a88130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:53:25\\n\\r BIOS CRC passed (a242a9e8)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000041\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_61"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56505494d130)\\n[serial2console] loaded (0x56505494d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56505494d130)\\n[serial2tcp] loaded (0x56505494d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:53:25\\n\\r BIOS CRC passed (a242a9e8)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000134\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_62"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5610cc605130)\\n[serial2console] loaded (0x5610cc605130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5610cc605130)\\n[serial2tcp] loaded (0x5610cc605130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:53:49\\n\\r BIOS CRC passed (391a6cdb)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting froBIST-GENERATOR ticks: 00005012\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00008980\\nm serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_63"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x555efb29d130)\\n[serial2console] loaded (0x555efb29d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x555efb29d130)\\n[serial2tcp] loaded (0x555efb29d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:53:49\\n\\r BIOS CRC passed (391a6cdb)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBIST-GENERATOR ticks: 00004167\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00007893\\nBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_64"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1694: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1702: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1711: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1720: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1728: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1749: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1758: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1775: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1792: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1813: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1822: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1830: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1848: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1869: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1877: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1912: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7886: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7917: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7948: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7979: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8230: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8272: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55564546e130)\\n[serial2console] loaded (0x55564546e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55564546e130)\\n[serial2tcp] loaded (0x55564546e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:54:13\\n\\r BIOS CRC passed (7fa225a0)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000020\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_65"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1694: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1702: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1711: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1720: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1728: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1749: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1758: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1775: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1792: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1813: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1822: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1830: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1848: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1869: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1877: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1912: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7886: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7917: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7948: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7979: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8230: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8272: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b4fc854130)\\n[serial2console] loaded (0x55b4fc854130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b4fc854130)\\n[serial2tcp] loaded (0x55b4fc854130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:54:14\\n\\r BIOS CRC passed (91c076c4)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000282\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000273\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_66"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1978: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2016: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2063: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2127: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2153: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2191: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9014: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9103: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9192: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9281: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9718: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9760: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55f065786130)\\n[serial2console] loaded (0x55f065786130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55f065786130)\\n[serial2tcp] loaded (0x55f065786130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:54:35\\n\\r BIOS CRC passed (c766851f)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000122\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8288: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_67"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1978: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2016: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2063: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2127: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2153: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2191: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9014: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9103: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9192: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9281: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9718: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9760: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5558329c5130)\\n[serial2console] loaded (0x5558329c5130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5558329c5130)\\n[serial2tcp] loaded (0x5558329c5130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:54:35\\n\\r BIOS CRC passed (c766851f)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000282\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000841\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8288: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_68"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1937: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2001: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2090: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8782: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8871: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8960: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9049: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9448: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9490: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56454d622130)\\n[serial2console] loaded (0x56454d622130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56454d622130)\\n[serial2tcp] loaded (0x56454d622130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:54:58\\n\\r BIOS CRC passed (3b3831fb)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000013\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8056: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_69"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1937: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2001: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2090: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8782: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8871: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8960: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9049: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9448: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9490: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5567abb9e130)\\n[serial2console] loaded (0x5567abb9e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5567abb9e130)\\n[serial2tcp] loaded (0x5567abb9e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:54:58\\n\\r BIOS CRC passed (3b3831fb)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000806\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000284\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8056: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_70"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2174: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2187: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2212: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2221: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2230: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2315: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2358: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2366: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2387: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9910: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10089: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10268: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10447: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11064: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11106: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e0bb691130)\\n[serial2console] loaded (0x55e0bb691130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e0bb691130)\\n[serial2tcp] loaded (0x55e0bb691130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:55:20\\n\\r BIOS CRC passed (a859ba83)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000115\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_71"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2174: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2187: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2212: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2221: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2230: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2315: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2358: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2366: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2387: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9910: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10089: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10268: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10447: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11064: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11106: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55ed3b200130)\\n[serial2console] loaded (0x55ed3b200130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55ed3b200130)\\n[serial2tcp] loaded (0x55ed3b200130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:55:20\\n\\r BIOS CRC passed (a859ba83)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000806\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000836\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_72"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2577: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2594: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2687: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2704: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2728: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2745: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2838: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2855: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2879: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2989: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3030: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3071: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3181: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3222: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3246: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3308: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3373: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3397: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3414: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3442: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3459: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3483: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3500: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3524: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3565: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3610: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3634: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3651: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3675: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3716: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3744: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3761: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14761: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14792: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14823: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14854: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14885: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14916: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14947: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14978: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15145: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15187: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5637eb58e130)\\n[serial2console] loaded (0x5637eb58e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5637eb58e130)\\n[serial2tcp] loaded (0x5637eb58e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:55:45\\n\\r BIOS CRC passed (4f2bc75b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00002606\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00018408\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13232: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_73"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2823: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2888: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2974: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3056: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3142: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3207: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3293: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3341: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3358: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3444: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3492: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3509: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3595: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3660: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3811: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3897: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15837: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15926: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16015: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16104: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16193: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16282: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16371: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16460: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16787: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16829: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5648a6d52130)\\n[serial2console] loaded (0x5648a6d52130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5648a6d52130)\\n[serial2tcp] loaded (0x5648a6d52130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:55:45\\n\\r BIOS CRC passed (4f2bc75b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00002389\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00028586\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14286: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_74"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2780: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2828: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2931: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2979: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3130: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3147: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3175: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3281: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3298: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3326: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3367: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3408: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3432: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3449: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3477: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3494: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3535: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3583: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3600: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3628: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3686: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3710: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3734: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3751: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3885: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3902: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15533: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15622: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15711: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15800: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15889: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15978: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16067: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16156: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16439: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16481: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a7852a3130)\\n[serial2console] loaded (0x55a7852a3130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a7852a3130)\\n[serial2tcp] loaded (0x55a7852a3130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:56:23\\n\\r BIOS CRC passed (4e883f21)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00023243\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00027618\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13982: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_75"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3074: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3091: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3160: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3177: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3225: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3242: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3270: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3311: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3328: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3352: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3393: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3421: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3438: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3462: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3479: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3503: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3527: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3544: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3572: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3589: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3613: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3630: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3654: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3678: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3695: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3723: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3740: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3764: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3829: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3846: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3915: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3932: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3956: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4083: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4107: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4176: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16605: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16784: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16963: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17142: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17321: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17500: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17679: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17858: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18333: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18375: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Trace__2.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x557b33dca130)\\n[serial2console] loaded (0x557b33dca130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x557b33dca130)\\n[serial2tcp] loaded (0x557b33dca130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:56:26\\n\\r BIOS CRC passed (387390a7)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00008027\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00028259\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15032: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_76"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2580: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2597: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2621: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2662: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2731: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2748: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2813: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2882: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2899: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2923: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2964: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3033: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3074: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3160: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3225: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3266: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3311: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3335: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3352: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3400: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3417: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3445: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3462: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3486: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3503: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3527: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3551: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3568: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3596: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3613: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3637: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3654: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3678: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3702: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3719: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3747: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3764: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14763: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14794: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14825: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14856: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14887: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14918: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14949: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14980: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15147: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15189: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b6d800c130)\\n[serial2console] loaded (0x55b6d800c130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b6d800c130)\\n[serial2tcp] loaded (0x55b6d800c130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:57:03\\n\\r BIOS CRC passed (a3b87821)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBootiBIST-GENERATOR ticks: 00004207\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00004168\\nng from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13234: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_77"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2843: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2867: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2908: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2936: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2994: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3059: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3169: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3210: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3344: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3389: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3471: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3495: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3512: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3540: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3557: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3581: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3598: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3646: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3663: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3749: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3814: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3859: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4010: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15809: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15898: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15987: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16076: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16165: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16254: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16343: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16432: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16759: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16801: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5558ab09b130)\\n[serial2console] loaded (0x5558ab09b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5558ab09b130)\\n[serial2tcp] loaded (0x5558ab09b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:57:10\\n\\r BIOS CRC passed (540772fb)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00004207\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005982\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14258: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_78"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2783: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2807: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2831: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2848: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2876: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2893: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2982: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3027: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3068: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3178: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3219: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3284: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3301: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3370: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3387: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3411: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3435: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3452: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3480: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3497: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3521: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3538: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3562: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3586: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3603: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3631: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3648: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3672: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3689: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3713: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3737: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3754: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3782: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3799: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3823: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3888: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15505: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15594: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15683: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15772: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15861: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15950: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16039: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16128: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16411: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16453: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x556897e2e130)\\n[serial2console] loaded (0x556897e2e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x556897e2e130)\\n[serial2tcp] loaded (0x556897e2e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:57:38\\n\\r BIOS CRC passed (3b031bd0)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00006132\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00004126\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13954: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_79"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3029: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3053: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3122: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3139: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3331: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3424: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3441: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3465: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3482: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3506: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3575: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3592: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3616: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3633: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3657: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3726: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3743: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3767: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3808: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3877: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3918: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4045: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4110: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4196: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16551: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16730: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16909: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17088: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17267: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17446: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17625: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17804: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18279: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18321: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_sim__10__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Trace__2.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b3d4238130)\\n[serial2console] loaded (0x55b3d4238130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b3d4238130)\\n[serial2tcp] loaded (0x55b3d4238130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:57:51\\n\\r BIOS CRC passed (fc6bb772)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q BIST-GENERATOR ticks: 00006132\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005973\\nor ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14978: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_80"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1727: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1754: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1801: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1812: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1828: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1855: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1871: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1882: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1902: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1929: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1940: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1956: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1972: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2030: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2057: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8051: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8082: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8113: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8144: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8311: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8353: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55c2a10f9130)\\n[serial2console] loaded (0x55c2a10f9130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55c2a10f9130)\\n[serial2tcp] loaded (0x55c2a10f9130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:58:16\\n\\r BIOS CRC passed (13bc9f68)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot cBIST-GENERATOR ticks: 00003173\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00014360\\nompletely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7456: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_81"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1957: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2186: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2244: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9031: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9120: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9209: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9298: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9625: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9667: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x557ed51f5130)\\n[serial2console] loaded (0x557ed51f5130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x557ed51f5130)\\n[serial2tcp] loaded (0x557ed51f5130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:58:31\\n\\r BIOS CRC passed (4a837ba0)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00002593\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00023660\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_82"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1897: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1908: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1940: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1982: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2083: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2110: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2142: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2153: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2243: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8727: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8816: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8905: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8994: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9319: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5622563db130)\\n[serial2console] loaded (0x5622563db130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5622563db130)\\n[serial2tcp] loaded (0x5622563db130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:58:34\\n\\r BIOS CRC passed (72af2ed1)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00018663\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00022929\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8118: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_83"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2127: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2138: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2181: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2212: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2239: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2313: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2356: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2372: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2383: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2414: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2441: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2457: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2473: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2504: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9703: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9882: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10061: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10240: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10715: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10757: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x559e849f9130)\\n[serial2console] loaded (0x559e849f9130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x559e849f9130)\\n[serial2tcp] loaded (0x559e849f9130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:58:54\\n\\r BIOS CRC passed (fe539a44)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00009886\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00027513\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9080: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_84"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1730: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1757: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1831: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1885: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1932: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2033: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2076: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2107: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8053: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8084: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8115: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8146: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8313: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8355: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a3a8102130)\\n[serial2console] loaded (0x55a3a8102130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a3a8102130)\\n[serial2tcp] loaded (0x55a3a8102130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:58:57\\n\\r BIOS CRC passed (e9b7a96b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\nBIST-GENERATOR ticks: 00003465\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00003428\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7458: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_85"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1960: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2045: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2061: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2088: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2146: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2205: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2306: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2348: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9003: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9092: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9181: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9270: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9597: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9639: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5559c52d7130)\\n[serial2console] loaded (0x5559c52d7130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5559c52d7130)\\n[serial2tcp] loaded (0x5559c52d7130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:59:18\\n\\r BIOS CRC passed (769f4f97)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from BIST-GENERATOR ticks: 00003465\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005750\\nserial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8394: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_86"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1974: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2001: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2102: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2156: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2176: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2187: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2203: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2214: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2230: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2246: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2277: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8699: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8788: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8877: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8966: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9249: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9291: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55f0e9e1a130)\\n[serial2console] loaded (0x55f0e9e1a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55f0e9e1a130)\\n[serial2tcp] loaded (0x55f0e9e1a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:59:19\\n\\r BIOS CRC passed (cd13a34d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from BIST-GENERATOR ticks: 00005776\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00003431\\nserial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8090: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_87"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2130: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2215: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2231: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2242: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2258: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2305: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2359: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2375: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2417: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2444: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2460: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2476: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2487: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2507: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9649: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9828: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10007: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10186: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10661: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10703: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5587a39b6130)\\n[serial2console] loaded (0x5587a39b6130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5587a39b6130)\\n[serial2tcp] loaded (0x5587a39b6130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:59:41\\n\\r BIOS CRC passed (3619bba5)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00005776\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005749\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9026: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_88"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1674: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1683: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1692: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1713: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1721: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1730: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1747: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1764: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1777: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1785: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1811: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1828: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1875: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1892: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7666: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7697: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7728: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7759: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7981: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8023: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5596cb808130)\\n[serial2console] loaded (0x5596cb808130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5596cb808130)\\n[serial2tcp] loaded (0x5596cb808130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 18:59:42\\n\\r BIOS CRC passed (605f987b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort BIST-GENERATOR ticks: 00004236\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00013679\\nboot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:6952: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_89"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1902: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1928: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2030: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2048: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2056: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8642: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8731: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8820: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8909: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9291: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9333: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55ec68023130)\\n[serial2console] loaded (0x55ec68023130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55ec68023130)\\n[serial2tcp] loaded (0x55ec68023130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 19:00:03\\n\\r BIOS CRC passed (5dc0aaa5)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00003136\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00022585\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7916: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_90"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1834: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1851: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1860: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1868: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1889: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1906: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1915: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1932: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1979: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2043: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8338: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8427: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8516: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8605: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8943: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8985: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e7babdc130)\\n[serial2console] loaded (0x55e7babdc130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e7babdc130)\\n[serial2tcp] loaded (0x55e7babdc130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 19:00:05\\n\\r BIOS CRC passed (d4a48816)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00017899\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00022119\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7612: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_91"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2088: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2160: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2181: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2207: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2224: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2262: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2301: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2309: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9310: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9489: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9668: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9847: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10377: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10419: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55adff4e3130)\\n[serial2console] loaded (0x55adff4e3130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55adff4e3130)\\n[serial2tcp] loaded (0x55adff4e3130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 19:00:24\\n\\r BIOS CRC passed (82027bcd)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00012392\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00033006\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8572: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_92"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1677: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1686: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1695: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1703: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1716: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1733: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1750: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1759: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1767: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1780: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1788: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1814: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1823: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1831: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1844: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1852: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1869: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1878: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1908: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7668: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7699: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7730: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7761: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7983: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8025: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55aa300ad130)\\n[serial2console] loaded (0x55aa300ad130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55aa300ad130)\\n[serial2tcp] loaded (0x55aa300ad130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 19:00:26\\n\\r BIOS CRC passed (4c0e9863)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ===BIST-GENERATOR ticks: 00002617\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002574\\n===============--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:6954: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_93"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1897: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1923: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1931: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1978: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1995: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2016: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2033: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2059: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2123: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8614: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8703: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8792: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8881: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9263: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9305: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x560014778130)\\n[serial2console] loaded (0x560014778130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x560014778130)\\n[serial2tcp] loaded (0x560014778130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 19:00:46\\n\\r BIOS CRC passed (1eef1e77)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBIST-GENERATOR ticks: 00002617\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005244\\nBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7888: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_94"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1854: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1871: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1892: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1901: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1918: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1956: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1973: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1982: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2020: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2029: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2046: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2063: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2076: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8310: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8915: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8957: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55dd7ae54130)\\n[serial2console] loaded (0x55dd7ae54130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55dd7ae54130)\\n[serial2tcp] loaded (0x55dd7ae54130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 19:00:47\\n\\r BIOS CRC passed (79e96fa0)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBIST-GENERATOR ticks: 00005285\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002574\\nBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7584: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_95"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2091: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2146: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2155: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2176: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2210: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2219: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2304: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9435: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9614: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9793: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10323: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10365: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x561e46b5e130)\\n[serial2console] loaded (0x561e46b5e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x561e46b5e130)\\n[serial2tcp] loaded (0x561e46b5e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 12 2020 19:01:08\\n\\r BIOS CRC passed (2d9a74b6)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 5097b7ae\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00005285\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005256\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8518: Verilog $finish\\n\\n'"}] \ No newline at end of file +[{"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_0"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\n CC umodsi3.o\\n CC udivsi3.o\\n CC divsi3.o\\n CC modsi3.o\\n CC comparesf2.o\\n CC comparedf2.o\\n CC negsf2.o\\n CC negdf2.o\\n CC addsf3.o\\n CC subsf3.o\\n CC mulsf3.o\\n CC divsf3.o\\n CC lshrdi3.o\\n CC muldi3.o\\n CC divdi3.o\\n CC ashldi3.o\\n CC ashrdi3.o\\n CC udivmoddi4.o\\n CC floatsisf.o\\n CC floatunsisf.o\\n CC fixsfsi.o\\n CC fixdfdi.o\\n CC fixunssfsi.o\\n CC fixunsdfdi.o\\n CC adddf3.o\\n CC subdf3.o\\n CC muldf3.o\\n CC divdf3.o\\n CC floatsidf.o\\n CC floatunsidf.o\\n CC floatdidf.o\\n CC fixdfsi.o\\n CC fixunsdfsi.o\\n CC clzsi2.o\\n CC ctzsi2.o\\n CC udivdi3.o\\n CC umoddi3.o\\n CC moddi3.o\\n CC ucmpdi2.o\\n CC mulsi3.o\\n AR libcompiler_rt.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC crt0.o\\n CC exception.o\\n CC libc.o\\n CC errno.o\\n CC crc16.o\\n CC crc32.o\\n CC console.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC qsort.o\\n CC strtod.o\\n CC spiflash.o\\n CC strcasecmp.o\\n CC i2c.o\\n CC div64.o\\n CC progress.o\\n CC memtest.o\\n CC sim_debug.o\\n CC vsnprintf.o\\n AR libbase.a\\n CC vsnprintf-nofloat.o\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC tftp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\n CC ffunicode.o\\n CC ff.o\\n AR libfatfs.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot-helper.o\\n CC boot.o\\n CC helpers.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n CC complete.o\\n CC readline.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/../.. -o xgmii_ethernet.o /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,xgmii_ethernet.so -o xgmii_ethernet.so xgmii_ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/ethernet/../.. -o ethernet.o /home/travis/litex/litex/build/sim/core/modules/ethernet/ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,ethernet.so -o ethernet.so ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2console/../.. -o serial2console.o /home/travis/litex/litex/build/sim/core/modules/serial2console/serial2console.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2console.so -o serial2console.so serial2console.o\\nrm serial2console.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2tcp/../.. -o serial2tcp.o /home/travis/litex/litex/build/sim/core/modules/serial2tcp/serial2tcp.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2tcp.so -o serial2tcp.so serial2tcp.o\\nrm serial2tcp.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/clocker/../.. -o clocker.o /home/travis/litex/litex/build/sim/core/modules/clocker/clocker.c\\ncc -levent -shared -fPIC -Wl,-soname,clocker.so -o clocker.so clocker.o\\nrm clocker.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/spdeeprom/../.. -o spdeeprom.o /home/travis/litex/litex/build/sim/core/modules/spdeeprom/spdeeprom.c\\ncc -levent -shared -fPIC -Wl,-soname,spdeeprom.so -o spdeeprom.so spdeeprom.o\\nrm spdeeprom.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55c9f0148130)\\n[serial2console] loaded (0x55c9f0148130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55c9f0148130)\\n[serial2tcp] loaded (0x55c9f0148130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:29:58\\n\\r BIOS CRC passed (41f07f4c)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000034\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_1"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\n CC umodsi3.o\\n CC udivsi3.o\\n CC divsi3.o\\n CC modsi3.o\\n CC comparesf2.o\\n CC comparedf2.o\\n CC negsf2.o\\n CC negdf2.o\\n CC addsf3.o\\n CC subsf3.o\\n CC mulsf3.o\\n CC divsf3.o\\n CC lshrdi3.o\\n CC muldi3.o\\n CC divdi3.o\\n CC ashldi3.o\\n CC ashrdi3.o\\n CC udivmoddi4.o\\n CC floatsisf.o\\n CC floatunsisf.o\\n CC fixsfsi.o\\n CC fixdfdi.o\\n CC fixunssfsi.o\\n CC fixunsdfdi.o\\n CC adddf3.o\\n CC subdf3.o\\n CC muldf3.o\\n CC divdf3.o\\n CC floatsidf.o\\n CC floatunsidf.o\\n CC floatdidf.o\\n CC fixdfsi.o\\n CC fixunsdfsi.o\\n CC clzsi2.o\\n CC ctzsi2.o\\n CC udivdi3.o\\n CC umoddi3.o\\n CC moddi3.o\\n CC ucmpdi2.o\\n CC mulsi3.o\\n AR libcompiler_rt.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC crt0.o\\n CC exception.o\\n CC libc.o\\n CC errno.o\\n CC crc16.o\\n CC crc32.o\\n CC console.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC qsort.o\\n CC strtod.o\\n CC spiflash.o\\n CC strcasecmp.o\\n CC i2c.o\\n CC div64.o\\n CC progress.o\\n CC memtest.o\\n CC sim_debug.o\\n CC vsnprintf.o\\n AR libbase.a\\n CC vsnprintf-nofloat.o\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC tftp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\n CC ffunicode.o\\n CC ff.o\\n AR libfatfs.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot-helper.o\\n CC boot.o\\n CC helpers.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n CC complete.o\\n CC readline.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/../.. -o xgmii_ethernet.o /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,xgmii_ethernet.so -o xgmii_ethernet.so xgmii_ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/travis/litex/litex/build/sim/core/modules/ethernet/../.. -o ethernet.o /home/travis/litex/litex/build/sim/core/modules/ethernet/ethernet.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o tapcfg.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/tapcfg.c\\ncc -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -c -o taplog.o /home/travis/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/lib/taplog.c\\ncc -levent -shared -fPIC -Wl,-soname,ethernet.so -o ethernet.so ethernet.o tapcfg.o taplog.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2console/../.. -o serial2console.o /home/travis/litex/litex/build/sim/core/modules/serial2console/serial2console.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2console.so -o serial2console.so serial2console.o\\nrm serial2console.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/serial2tcp/../.. -o serial2tcp.o /home/travis/litex/litex/build/sim/core/modules/serial2tcp/serial2tcp.c\\ncc -levent -shared -fPIC -Wl,-soname,serial2tcp.so -o serial2tcp.so serial2tcp.o\\nrm serial2tcp.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/clocker/../.. -o clocker.o /home/travis/litex/litex/build/sim/core/modules/clocker/clocker.c\\ncc -levent -shared -fPIC -Wl,-soname,clocker.so -o clocker.so clocker.o\\nrm clocker.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncc -c -Wall -O3 -ggdb -fPIC -Werror -I/home/travis/litex/litex/build/sim/core/modules/spdeeprom/../.. -o spdeeprom.o /home/travis/litex/litex/build/sim/core/modules/spdeeprom/spdeeprom.c\\ncc -levent -shared -fPIC -Wl,-soname,spdeeprom.so -o spdeeprom.so spdeeprom.o\\nrm spdeeprom.o\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55ec50101130)\\n[serial2console] loaded (0x55ec50101130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55ec50101130)\\n[serial2tcp] loaded (0x55ec50101130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:29:58\\n\\r BIOS CRC passed (41f07f4c)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000034\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_2"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x561307a34130)\\n[serial2console] loaded (0x561307a34130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x561307a34130)\\n[serial2tcp] loaded (0x561307a34130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:30:38\\n\\r BIOS CRC passed (c6d93d74)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000084\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000762\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_3"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2712: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3165: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3374: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3398: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3422: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3439: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3467: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3525: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3549: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3573: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3635: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3676: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3786: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14963: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14994: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15025: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15056: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15087: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15118: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15149: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15180: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15376: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15418: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x562a02a21130)\\n[serial2console] loaded (0x562a02a21130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x562a02a21130)\\n[serial2tcp] loaded (0x562a02a21130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:30:38\\n\\r BIOS CRC passed (c6d93d74)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000188\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000633\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:13434: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_4"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x556329d11130)\\n[serial2console] loaded (0x556329d11130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x556329d11130)\\n[serial2tcp] loaded (0x556329d11130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:31:16\\n\\r BIOS CRC passed (70e200aa)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000042\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_5"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55fa3ea81130)\\n[serial2console] loaded (0x55fa3ea81130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55fa3ea81130)\\n[serial2tcp] loaded (0x55fa3ea81130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:31:16\\n\\r BIOS CRC passed (70e200aa)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000136\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_6"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d9ed680130)\\n[serial2console] loaded (0x55d9ed680130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d9ed680130)\\n[serial2tcp] loaded (0x55d9ed680130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:31:56\\n\\r BIOS CRC passed (18894f77)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000074\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001060\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_7"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2870: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3021: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3172: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3405: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3474: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3491: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3539: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3556: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3584: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3601: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3625: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3735: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3776: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3817: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16205: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16294: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16383: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16472: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16561: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16650: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16739: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16828: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17210: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17252: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e945649130)\\n[serial2console] loaded (0x55e945649130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e945649130)\\n[serial2tcp] loaded (0x55e945649130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:31:57\\n\\r BIOS CRC passed (d88ec523)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000126\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000923\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14654: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_8"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x556751f3d130)\\n[serial2console] loaded (0x556751f3d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x556751f3d130)\\n[serial2tcp] loaded (0x556751f3d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:32:38\\n\\r BIOS CRC passed (afa3fae8)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000042\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_9"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564cae39e130)\\n[serial2console] loaded (0x564cae39e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564cae39e130)\\n[serial2tcp] loaded (0x564cae39e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:32:38\\n\\r BIOS CRC passed (afa3fae8)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000042\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_10"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5625a6efd130)\\n[serial2console] loaded (0x5625a6efd130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5625a6efd130)\\n[serial2tcp] loaded (0x5625a6efd130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:33:20\\n\\r BIOS CRC passed (415146a4)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000878\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001020\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_11"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2816: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2833: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2857: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2926: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3269: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3286: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3351: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3420: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3437: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3485: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3502: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3571: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3588: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3612: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3636: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3653: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3722: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3739: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3787: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15973: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16062: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16151: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16240: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16329: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16418: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16507: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16596: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16940: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16982: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d30a74d130)\\n[serial2console] loaded (0x55d30a74d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d30a74d130)\\n[serial2tcp] loaded (0x55d30a74d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:33:20\\n\\r BIOS CRC passed (415146a4)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000706\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000900\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_12"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56290667f130)\\n[serial2console] loaded (0x56290667f130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56290667f130)\\n[serial2tcp] loaded (0x56290667f130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:34:01\\n\\r BIOS CRC passed (d7e9c354)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000050\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_13"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b0779dd130)\\n[serial2console] loaded (0x55b0779dd130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b0779dd130)\\n[serial2tcp] loaded (0x55b0779dd130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:34:02\\n\\r BIOS CRC passed (4c905be9)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000144\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_14"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55abba3ba130)\\n[serial2console] loaded (0x55abba3ba130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55abba3ba130)\\n[serial2tcp] loaded (0x55abba3ba130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:34:45\\n\\r BIOS CRC passed (097ea95b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000728\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001188\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_15"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3149: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3194: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3300: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3362: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3451: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3496: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3513: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3602: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3647: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3664: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3753: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4100: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4158: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4223: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17211: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17390: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17569: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17748: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17927: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18106: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18285: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18464: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19026: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19068: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56305fc6f130)\\n[serial2console] loaded (0x56305fc6f130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56305fc6f130)\\n[serial2tcp] loaded (0x56305fc6f130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:34:46\\n\\r BIOS CRC passed (920731e6)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000695\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001189\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15638: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_16"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2646: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2670: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2687: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2715: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2821: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2838: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2972: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2989: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3123: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3168: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3250: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3319: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3336: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3401: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3425: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3442: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3470: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3487: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3511: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3528: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3552: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3576: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3621: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3638: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3662: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3679: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3703: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3727: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3744: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14981: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15012: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15043: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15074: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15105: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15136: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15167: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15198: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15394: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15436: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x563954918130)\\n[serial2console] loaded (0x563954918130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x563954918130)\\n[serial2tcp] loaded (0x563954918130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:35:30\\n\\r BIOS CRC passed (96189c67)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000030\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:13452: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_17"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2646: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2670: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2687: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2715: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2821: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2838: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2972: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2989: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3123: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3168: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3250: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3319: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3336: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3401: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3425: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3442: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3470: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3487: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3511: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3528: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3552: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3576: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3621: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3638: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3662: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3679: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3703: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3727: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3744: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14981: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15012: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15043: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15074: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15105: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15136: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15167: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15198: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15394: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15436: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5601da58a130)\\n[serial2console] loaded (0x5601da58a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5601da58a130)\\n[serial2tcp] loaded (0x5601da58a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:35:30\\n\\r BIOS CRC passed (96189c67)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000041\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000053\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13452: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_18"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3175: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3326: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3367: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3408: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3436: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3453: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3477: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3494: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3542: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3587: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3604: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3628: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3693: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3710: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3844: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3889: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3906: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3995: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4040: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4057: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16209: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16298: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16387: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16476: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16565: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16654: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16743: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16832: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17214: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17256: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55cfa0806130)\\n[serial2console] loaded (0x55cfa0806130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55cfa0806130)\\n[serial2tcp] loaded (0x55cfa0806130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:36:08\\n\\r BIOS CRC passed (c81dc379)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000132\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_19"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3175: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3326: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3367: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3408: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3436: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3453: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3477: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3494: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3542: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3587: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3604: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3628: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3693: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3710: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3844: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3889: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3906: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3995: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4040: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4057: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16209: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16298: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16387: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16476: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16565: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16654: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16743: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16832: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17214: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17256: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56134dd5b130)\\n[serial2console] loaded (0x56134dd5b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56134dd5b130)\\n[serial2tcp] loaded (0x56134dd5b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:36:09\\n\\r BIOS CRC passed (081a492d)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000041\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000157\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_20"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2860: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2901: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2929: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2946: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3121: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3138: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3186: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3203: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3231: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3272: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3289: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3313: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3354: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3382: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3399: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3423: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3440: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3464: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3488: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3533: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3550: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3574: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3591: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3615: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3639: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3656: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3701: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3742: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3790: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3807: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3852: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3876: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3893: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15977: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16066: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16155: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16244: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16333: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16422: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16511: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16600: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16944: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16986: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5651a148b130)\\n[serial2console] loaded (0x5651a148b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5651a148b130)\\n[serial2tcp] loaded (0x5651a148b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:36:49\\n\\r BIOS CRC passed (607106f0)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000017\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14426: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_21"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2860: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2901: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2929: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2946: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3121: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3138: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3186: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3203: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3231: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3272: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3289: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3313: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3354: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3382: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3399: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3423: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3440: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3464: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3488: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3533: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3550: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3574: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3591: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3615: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3639: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3656: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3684: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3701: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3742: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3790: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3807: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3835: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3852: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3876: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3893: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15977: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16066: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16155: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16244: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16333: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16422: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16511: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16600: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16944: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16986: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x562fa7874130)\\n[serial2console] loaded (0x562fa7874130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x562fa7874130)\\n[serial2tcp] loaded (0x562fa7874130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:36:51\\n\\r BIOS CRC passed (ba3ed972)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000117\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000048\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14426: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_22"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3169: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3197: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3214: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3348: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3365: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3389: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3454: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3471: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3499: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3540: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3557: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3581: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3650: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3801: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3859: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4010: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4161: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:4271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17205: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17384: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17563: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17742: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:17921: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18100: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18279: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:18458: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19020: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:19062: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55ea17907130)\\n[serial2console] loaded (0x55ea17907130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55ea17907130)\\n[serial2tcp] loaded (0x55ea17907130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:37:31\\n\\r BIOS CRC passed (3f65d1af)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000024\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000119\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15632: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_23"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3169: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3197: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3214: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3348: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3365: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3389: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3454: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3471: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3499: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3540: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3557: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3581: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3605: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3650: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3667: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3801: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3818: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3859: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4010: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4161: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4185: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17205: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17384: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17563: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17742: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17921: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18100: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18279: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18458: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19020: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:19062: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x562ae05f5130)\\n[serial2console] loaded (0x562ae05f5130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x562ae05f5130)\\n[serial2tcp] loaded (0x562ae05f5130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:37:32\\n\\r BIOS CRC passed (a41c4912)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\rBIST-GENERATOR ticks: 00000117\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000152\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15632: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_24"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x560db7965130)\\n[serial2console] loaded (0x560db7965130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x560db7965130)\\n[serial2tcp] loaded (0x560db7965130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:38:17\\n\\r BIOS CRC passed (1bd8cafd)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000027\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_25"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e9af734130)\\n[serial2console] loaded (0x55e9af734130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e9af734130)\\n[serial2tcp] loaded (0x55e9af734130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:38:18\\n\\r BIOS CRC passed (53ac356e)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000027\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_26"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55f6cab36130)\\n[serial2console] loaded (0x55f6cab36130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55f6cab36130)\\n[serial2tcp] loaded (0x55f6cab36130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:38:39\\n\\r BIOS CRC passed (255bb7f8)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000204\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001184\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_27"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1752: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1795: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1806: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1981: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8253: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8315: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8346: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8542: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8584: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e2a35c9130)\\n[serial2console] loaded (0x55e2a35c9130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e2a35c9130)\\n[serial2tcp] loaded (0x55e2a35c9130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:38:39\\n\\r BIOS CRC passed (255bb7f8)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000396\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000988\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7658: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_28"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5639bc195130)\\n[serial2console] loaded (0x5639bc195130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5639bc195130)\\n[serial2tcp] loaded (0x5639bc195130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:39:01\\n\\r BIOS CRC passed (c476d833)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000035\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_29"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x558dd8d19130)\\n[serial2console] loaded (0x558dd8d19130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x558dd8d19130)\\n[serial2tcp] loaded (0x558dd8d19130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:39:02\\n\\r BIOS CRC passed (d392eb1c)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000129\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_30"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55826e5af130)\\n[serial2console] loaded (0x55826e5af130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55826e5af130)\\n[serial2tcp] loaded (0x55826e5af130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:39:25\\n\\r BIOS CRC passed (8aad0fd4)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000166\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001801\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_31"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2217: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2318: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2350: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2381: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2392: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9666: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10048: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10090: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56467a25b130)\\n[serial2console] loaded (0x56467a25b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56467a25b130)\\n[serial2tcp] loaded (0x56467a25b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:39:25\\n\\r BIOS CRC passed (8aad0fd4)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000269\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001550\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8790: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_32"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55dbf1f9e130)\\n[serial2console] loaded (0x55dbf1f9e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55dbf1f9e130)\\n[serial2tcp] loaded (0x55dbf1f9e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:39:49\\n\\r BIOS CRC passed (59c177fd)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000035\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_33"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55aa1f6a5130)\\n[serial2console] loaded (0x55aa1f6a5130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55aa1f6a5130)\\n[serial2tcp] loaded (0x55aa1f6a5130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:39:49\\n\\r BIOS CRC passed (59c177fd)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000035\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_34"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5574a59cd130)\\n[serial2console] loaded (0x5574a59cd130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5574a59cd130)\\n[serial2tcp] loaded (0x5574a59cd130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:40:12\\n\\r BIOS CRC passed (a3e2f5dc)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00001434\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001723\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_35"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2004: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2078: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2206: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2226: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2253: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2264: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2307: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2327: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2338: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9167: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9345: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9434: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9778: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9820: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55e662387130)\\n[serial2console] loaded (0x55e662387130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55e662387130)\\n[serial2tcp] loaded (0x55e662387130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:40:12\\n\\r BIOS CRC passed (a3e2f5dc)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00001232\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00001499\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8558: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_36"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55f0f3d6d130)\\n[serial2console] loaded (0x55f0f3d6d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55f0f3d6d130)\\n[serial2tcp] loaded (0x55f0f3d6d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:40:36\\n\\r BIOS CRC passed (ed39223b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000043\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_37"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55fe2872c130)\\n[serial2console] loaded (0x55fe2872c130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55fe2872c130)\\n[serial2tcp] loaded (0x55fe2872c130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:40:36\\n\\r BIOS CRC passed (ed39223b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000137\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_38"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56475c97f130)\\n[serial2console] loaded (0x56475c97f130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56475c97f130)\\n[serial2tcp] loaded (0x56475c97f130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:41:01\\n\\r BIOS CRC passed (4460b263)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--=BIST-GENERATOR ticks: 00001371\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002276\\n============= \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_39"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2357: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2377: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2388: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2404: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2415: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2431: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2458: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2478: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2489: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2505: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2516: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2532: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2579: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2590: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10309: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10488: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10667: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10846: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11408: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11450: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5580d86fa130)\\n[serial2console] loaded (0x5580d86fa130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5580d86fa130)\\n[serial2tcp] loaded (0x5580d86fa130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:41:01\\n\\r BIOS CRC passed (4460b263)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r-BIST-GENERATOR ticks: 00001113\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002067\\n-============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9686: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_40"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1782: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1809: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1829: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1867: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1899: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1910: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1957: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8271: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8302: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8333: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8364: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8560: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8602: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564fe7c17130)\\n[serial2console] loaded (0x564fe7c17130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564fe7c17130)\\n[serial2tcp] loaded (0x564fe7c17130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:41:26\\n\\r BIOS CRC passed (1d5f56ab)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000023\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7676: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_41"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1782: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1798: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1809: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1829: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1867: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1899: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1910: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1957: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8271: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8302: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8333: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8364: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8560: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8602: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5556b2291130)\\n[serial2console] loaded (0x5556b2291130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5556b2291130)\\n[serial2tcp] loaded (0x5556b2291130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:41:26\\n\\r BIOS CRC passed (1d5f56ab)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000069\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000082\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7676: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_42"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2061: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2092: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2220: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2321: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2353: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2395: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9403: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9492: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9581: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9670: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10052: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10094: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x562ad2a93130)\\n[serial2console] loaded (0x562ad2a93130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x562ad2a93130)\\n[serial2tcp] loaded (0x562ad2a93130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:41:48\\n\\r BIOS CRC passed (625bf177)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000125\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8794: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_43"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2061: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2092: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2220: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2321: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2353: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2364: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2395: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9403: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9492: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9581: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9670: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10052: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10094: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a5c2270130)\\n[serial2console] loaded (0x55a5c2270130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a5c2270130)\\n[serial2tcp] loaded (0x55a5c2270130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:41:48\\n\\r BIOS CRC passed (625bf177)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000069\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000250\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8794: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_44"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1964: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2027: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2139: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2155: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2267: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2341: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9171: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9260: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9349: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9438: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9782: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9824: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55619e546130)\\n[serial2console] loaded (0x55619e546130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55619e546130)\\n[serial2tcp] loaded (0x55619e546130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:42:11\\n\\r BIOS CRC passed (42c047de)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000014\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8562: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_45"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1964: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2027: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2038: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2054: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2139: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2155: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2182: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2229: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2267: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2310: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2330: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2341: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9171: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9260: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9349: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9438: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9782: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9824: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a1208ec130)\\n[serial2console] loaded (0x55a1208ec130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a1208ec130)\\n[serial2tcp] loaded (0x55a1208ec130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:42:11\\n\\r BIOS CRC passed (42c047de)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\rBIST-GENERATOR ticks: 00000209\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000077\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8562: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_46"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2205: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2232: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2306: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2380: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2407: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2418: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2434: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2481: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2492: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2519: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2535: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2551: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2562: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2582: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10303: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10482: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10661: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10840: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11402: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11444: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5565c60ae130)\\n[serial2console] loaded (0x5565c60ae130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5565c60ae130)\\n[serial2tcp] loaded (0x5565c60ae130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:42:35\\n\\r BIOS CRC passed (0c1b9039)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\rBIST-GENERATOR ticks: 00000020\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000126\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9680: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_47"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2205: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2232: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2306: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2333: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2360: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2380: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2391: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2407: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2418: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2434: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2450: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2461: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2481: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2492: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2508: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2519: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2535: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2551: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2562: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2582: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10303: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10482: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10661: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10840: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11402: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11444: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5630d275c130)\\n[serial2console] loaded (0x5630d275c130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5630d275c130)\\n[serial2tcp] loaded (0x5630d275c130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:42:35\\n\\r BIOS CRC passed (0c1b9039)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 239KiB/s\\n\\r\\nBIST-GENERATOR ticks: 00000234\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000245\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9680: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_48"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d9bc252130)\\n[serial2console] loaded (0x55d9bc252130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d9bc252130)\\n[serial2tcp] loaded (0x55d9bc252130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:43:00\\n\\r BIOS CRC passed (59ff1cb6)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000024\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_49"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5567e9c95130)\\n[serial2console] loaded (0x5567e9c95130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5567e9c95130)\\n[serial2tcp] loaded (0x5567e9c95130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:43:00\\n\\r BIOS CRC passed (59ff1cb6)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000024\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_50"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x555860b6d130)\\n[serial2console] loaded (0x555860b6d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x555860b6d130)\\n[serial2tcp] loaded (0x555860b6d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:43:20\\n\\r BIOS CRC passed (685f9eba)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBootBIST-GENERATOR ticks: 00000852\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00004372\\n\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_51"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1717: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1725: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1755: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1789: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1819: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1827: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1836: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1853: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1938: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7868: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7899: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7930: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7961: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8212: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8254: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56030a891130)\\n[serial2console] loaded (0x56030a891130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56030a891130)\\n[serial2tcp] loaded (0x56030a891130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:43:20\\n\\r BIOS CRC passed (685f9eba)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1bBIST-GENERATOR ticks: 00001591\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00003673\\n[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7154: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_52"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d76d57c130)\\n[serial2console] loaded (0x55d76d57c130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d76d57c130)\\n[serial2tcp] loaded (0x55d76d57c130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:43:41\\n\\r BIOS CRC passed (5db86979)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000033\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_53"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x556c6c7a2130)\\n[serial2console] loaded (0x556c6c7a2130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x556c6c7a2130)\\n[serial2tcp] loaded (0x556c6c7a2130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:43:41\\n\\r BIOS CRC passed (5db86979)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000126\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_54"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x556db4f31130)\\n[serial2console] loaded (0x556db4f31130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x556db4f31130)\\n[serial2tcp] loaded (0x556db4f31130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:44:03\\n\\r BIOS CRC passed (8d01e33e)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--BIST-GENERATOR ticks: 00000682\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00006803\\n\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_55"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1967: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2124: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2167: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2188: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9010: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9099: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9188: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9714: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9756: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55efc46e2130)\\n[serial2console] loaded (0x55efc46e2130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55efc46e2130)\\n[serial2tcp] loaded (0x55efc46e2130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:44:03\\n\\r BIOS CRC passed (8d01e33e)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==========BIST-GENERATOR ticks: 00001051\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005803\\n========--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8284: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_56"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55687bdd3130)\\n[serial2console] loaded (0x55687bdd3130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55687bdd3130)\\n[serial2tcp] loaded (0x55687bdd3130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:44:25\\n\\r BIOS CRC passed (35c54381)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000032\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_57"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x563cf1195130)\\n[serial2console] loaded (0x563cf1195130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x563cf1195130)\\n[serial2tcp] loaded (0x563cf1195130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:44:25\\n\\r BIOS CRC passed (35c54381)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000032\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_58"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x562e62bc8130)\\n[serial2console] loaded (0x562e62bc8130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x562e62bc8130)\\n[serial2tcp] loaded (0x562e62bc8130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:44:47\\n\\r BIOS CRC passed (a928263b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ================BIST-GENERATOR ticks: 00005414\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00006448\\n==--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_59"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1904: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1942: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2023: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2032: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2049: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2105: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8778: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8867: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8956: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9045: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9444: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9486: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55ad0e1f4130)\\n[serial2console] loaded (0x55ad0e1f4130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55ad0e1f4130)\\n[serial2tcp] loaded (0x55ad0e1f4130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:44:47\\n\\r BIOS CRC passed (a928263b)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m =========BIST-GENERATOR ticks: 00004705\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005779\\n=========--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8052: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_60"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5628ddd20130)\\n[serial2console] loaded (0x5628ddd20130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5628ddd20130)\\n[serial2tcp] loaded (0x5628ddd20130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:45:09\\n\\r BIOS CRC passed (9a5d4cfa)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000041\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_61"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x563ed98c5130)\\n[serial2console] loaded (0x563ed98c5130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x563ed98c5130)\\n[serial2tcp] loaded (0x563ed98c5130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:45:09\\n\\r BIOS CRC passed (9a5d4cfa)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000134\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": true, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_62"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55825360d130)\\n[serial2console] loaded (0x55825360d130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55825360d130)\\n[serial2tcp] loaded (0x55825360d130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:45:33\\n\\r BIOS CRC passed (f3f0ee64)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting froBIST-GENERATOR ticks: 00005012\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00008980\\nm serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_63"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2171: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2209: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2218: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2256: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2299: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2363: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9916: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10095: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10274: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10453: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11070: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11112: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x561a94209130)\\n[serial2console] loaded (0x561a94209130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x561a94209130)\\n[serial2tcp] loaded (0x561a94209130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:45:33\\n\\r BIOS CRC passed (f3f0ee64)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBIST-GENERATOR ticks: 00004167\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00007893\\nBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9178: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_64"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1694: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1702: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1711: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1720: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1728: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1749: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1758: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1775: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1792: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1813: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1822: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1830: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1848: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1869: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1877: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1912: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7886: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7917: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7948: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7979: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8230: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8272: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bff151b130)\\n[serial2console] loaded (0x55bff151b130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bff151b130)\\n[serial2tcp] loaded (0x55bff151b130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:45:56\\n\\r BIOS CRC passed (817fd8ba)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000020\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_65"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1694: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1702: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1711: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1720: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1728: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1749: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1758: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1775: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1792: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1813: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1822: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1830: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1848: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1869: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1877: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1886: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1903: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1912: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7886: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7917: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7948: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7979: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8230: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8272: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a8eeeb1130)\\n[serial2console] loaded (0x55a8eeeb1130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a8eeeb1130)\\n[serial2tcp] loaded (0x55a8eeeb1130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:45:56\\n\\r BIOS CRC passed (817fd8ba)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000282\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000273\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_66"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1978: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2016: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2063: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2127: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2153: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2191: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9014: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9103: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9192: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9281: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9718: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9760: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x562edb2ba130)\\n[serial2console] loaded (0x562edb2ba130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x562edb2ba130)\\n[serial2tcp] loaded (0x562edb2ba130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:46:17\\n\\r BIOS CRC passed (7dbaff85)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000002\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000122\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8288: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_67"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1978: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2016: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2063: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2127: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2153: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2183: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2191: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9014: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9103: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9192: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9281: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9718: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9760: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a28f275130)\\n[serial2console] loaded (0x55a28f275130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a28f275130)\\n[serial2tcp] loaded (0x55a28f275130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:46:17\\n\\r BIOS CRC passed (7dbaff85)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000282\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000841\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8288: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_68"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1937: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2001: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2090: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8782: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8871: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8960: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9049: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9448: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9490: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d24cdcc130)\\n[serial2console] loaded (0x55d24cdcc130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d24cdcc130)\\n[serial2tcp] loaded (0x55d24cdcc130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:46:40\\n\\r BIOS CRC passed (e849e9ff)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000013\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8056: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_69"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1907: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1937: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2001: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2035: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2090: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2108: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2116: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8782: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8871: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8960: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9049: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9448: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9490: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5637770ce130)\\n[serial2console] loaded (0x5637770ce130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5637770ce130)\\n[serial2tcp] loaded (0x5637770ce130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:46:40\\n\\r BIOS CRC passed (e849e9ff)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000806\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000284\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8056: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_70"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2174: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2187: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2212: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2221: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2230: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2315: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2358: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2366: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2387: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9910: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10089: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10268: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10447: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11064: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:11106: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x563b5bcad130)\\n[serial2console] loaded (0x563b5bcad130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x563b5bcad130)\\n[serial2tcp] loaded (0x563b5bcad130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:47:01\\n\\r BIOS CRC passed (bb8f5260)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\rBIST-GENERATOR ticks: 00000018\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000115\\n\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"bist_random": false, "bist_length": 1024}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_71"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2174: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2187: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2212: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2221: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2230: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2251: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2259: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2268: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2315: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2323: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2358: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2366: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2387: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9910: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10089: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10268: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10447: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11064: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:11106: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5609bc8a6130)\\n[serial2console] loaded (0x5609bc8a6130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5609bc8a6130)\\n[serial2tcp] loaded (0x5609bc8a6130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:47:02\\n\\r BIOS CRC passed (1285c019)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\rBIST-GENERATOR ticks: 00000806\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00000836\\n--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9172: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_72"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2577: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2594: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2618: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2642: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2659: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2687: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2704: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2728: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2745: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2769: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2793: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2810: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2838: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2855: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2879: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2896: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2989: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3030: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3047: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3071: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3095: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3140: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3181: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3222: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3246: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3308: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3349: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3373: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3397: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3414: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3442: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3459: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3483: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3500: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3524: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3548: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3565: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3593: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3610: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3634: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3651: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3675: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3699: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3716: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3744: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3761: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14761: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14792: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14823: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14854: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14885: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14916: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14947: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14978: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15145: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15187: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d0f8a95130)\\n[serial2console] loaded (0x55d0f8a95130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d0f8a95130)\\n[serial2tcp] loaded (0x55d0f8a95130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:47:26\\n\\r BIOS CRC passed (d3ce44ca)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00002606\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00018408\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13232: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_73"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2823: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2888: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2974: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3015: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3056: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3125: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3142: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3166: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3207: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3235: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3252: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3276: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3293: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3341: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3358: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3427: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3444: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3468: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3492: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3509: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3537: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3554: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3578: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3595: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3619: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3643: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3660: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3688: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3705: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3729: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3746: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3811: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3856: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3880: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3897: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3921: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3990: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4007: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15837: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15926: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16015: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16104: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16193: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16282: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16371: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16460: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16787: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16829: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564198406130)\\n[serial2console] loaded (0x564198406130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564198406130)\\n[serial2tcp] loaded (0x564198406130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:47:26\\n\\r BIOS CRC passed (d3ce44ca)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00002389\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00028586\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14286: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_74"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2763: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2780: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2828: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2873: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2890: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2931: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2955: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2979: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3024: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3130: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3147: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3175: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3192: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3281: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3298: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3326: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3367: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3384: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3408: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3432: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3449: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3477: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3494: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3535: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3559: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3583: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3600: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3628: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3686: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3710: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3734: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3751: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3779: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3885: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3902: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3930: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15533: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15622: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15711: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15800: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15889: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15978: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16067: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16156: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16439: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16481: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bf04a39130)\\n[serial2console] loaded (0x55bf04a39130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bf04a39130)\\n[serial2tcp] loaded (0x55bf04a39130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:48:03\\n\\r BIOS CRC passed (8d10fcd9)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00023243\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00027618\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13982: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_75"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3074: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3091: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3119: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3160: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3177: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3225: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3242: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3270: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3311: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3328: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3352: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3393: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3421: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3438: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3462: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3479: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3503: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3527: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3544: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3572: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3589: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3613: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3630: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3654: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3678: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3695: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3723: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3740: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3764: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3829: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3846: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3915: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3932: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3956: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3980: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3997: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4066: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4083: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4107: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4131: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4148: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4176: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16605: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16784: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16963: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17142: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17321: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17500: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17679: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17858: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18333: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18375: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Trace__2.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x559eae873130)\\n[serial2console] loaded (0x559eae873130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x559eae873130)\\n[serial2tcp] loaded (0x559eae873130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:48:06\\n\\r BIOS CRC passed (fbeb535f)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00008027\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00028259\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15032: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_76"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2580: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2597: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2621: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2645: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2662: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2690: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2707: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2731: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2748: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2772: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2796: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2813: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2882: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2899: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2923: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2947: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2964: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3033: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3050: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3074: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3098: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3160: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3225: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3249: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3266: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3294: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3311: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3335: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3352: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3376: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3400: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3417: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3445: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3462: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3486: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3503: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3527: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3551: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3568: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3596: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3613: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3637: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3654: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3678: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3702: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3719: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3747: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3764: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14763: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14794: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14825: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14856: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14887: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14918: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14949: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:14980: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15147: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15189: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x555dd43a2130)\\n[serial2console] loaded (0x555dd43a2130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x555dd43a2130)\\n[serial2tcp] loaded (0x555dd43a2130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:48:42\\n\\r BIOS CRC passed (257c3950)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBootiBIST-GENERATOR ticks: 00004207\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00004168\\nng from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13234: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_77"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2826: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2843: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2867: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2891: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2908: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2936: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2977: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2994: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3018: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3059: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3128: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3169: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3210: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3238: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3279: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3296: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3320: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3344: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3361: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3389: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3447: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3471: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3495: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3512: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3540: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3557: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3581: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3598: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3622: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3646: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3663: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3691: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3708: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3732: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3749: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3814: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3859: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3883: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3993: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4010: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15809: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15898: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:15987: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16076: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16165: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16254: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16343: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16432: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16759: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16801: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5609fc9ea130)\\n[serial2console] loaded (0x5609fc9ea130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5609fc9ea130)\\n[serial2tcp] loaded (0x5609fc9ea130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:48:51\\n\\r BIOS CRC passed (d2c3338a)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00004207\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005982\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14258: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_78"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2766: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2783: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2807: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2831: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2848: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2876: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2893: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2917: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2934: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2982: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3027: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3068: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3150: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3178: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3195: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3219: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3284: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3301: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3346: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3370: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3387: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3411: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3435: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3452: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3480: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3497: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3521: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3538: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3562: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3586: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3603: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3631: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3648: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3672: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3689: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3713: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3737: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3754: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3782: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3799: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3823: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3840: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3864: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3888: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3933: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:3950: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15505: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15594: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15683: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15772: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15861: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:15950: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16039: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16128: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16411: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:16453: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55d0753aa130)\\n[serial2console] loaded (0x55d0753aa130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55d0753aa130)\\n[serial2tcp] loaded (0x55d0753aa130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:49:16\\n\\r BIOS CRC passed (a390a2f6)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00006132\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00004126\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:13954: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT41K128M16", "name": "test_79"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.12KiB \\t(69.13%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3029: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3053: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3122: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3139: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3180: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3273: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3331: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3355: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3379: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3396: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3424: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3441: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3465: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3482: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3506: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3530: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3547: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3575: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3592: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3616: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3633: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3657: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3681: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3698: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3726: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3743: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3767: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3808: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3832: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3877: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3918: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:3983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4045: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4110: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4151: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4179: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:4196: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16551: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16730: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:16909: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17088: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17267: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17446: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17625: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:17804: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18279: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:18321: Case values incompletely covered (example pattern 0x21)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_sim__6.cpp Vsim_sim__7.cpp Vsim_sim__8.cpp Vsim_sim__9.cpp Vsim_sim__10.cpp Vsim_sim__11.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_sim__5__Slow.cpp Vsim_sim__6__Slow.cpp Vsim_sim__7__Slow.cpp Vsim_sim__8__Slow.cpp Vsim_sim__9__Slow.cpp Vsim_sim__10__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Trace__2.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55815ab6e130)\\n[serial2console] loaded (0x55815ab6e130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55815ab6e130)\\n[serial2tcp] loaded (0x55815ab6e130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:49:29\\n\\r BIOS CRC passed (8dd7e4d5)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t524288KiB 32-bit @ 8MT/s (CL-6 CWL-5)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 252KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q BIST-GENERATOR ticks: 00006132\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005973\\nor ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:14978: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_80"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1727: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1754: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1770: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1781: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1801: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1812: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1828: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1839: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1855: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1871: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1882: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1902: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1929: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1940: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1956: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1972: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1983: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2030: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2057: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8051: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8082: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8113: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8144: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8311: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8353: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x558817dbd130)\\n[serial2console] loaded (0x558817dbd130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x558817dbd130)\\n[serial2tcp] loaded (0x558817dbd130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:49:53\\n\\r BIOS CRC passed (a2ca085f)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot cBIST-GENERATOR ticks: 00003173\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00014360\\nompletely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7456: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_81"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1957: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1968: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2000: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2011: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2031: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2058: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2085: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2101: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2132: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2159: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2186: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2202: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2213: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2233: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2244: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2260: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2287: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2303: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2314: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2334: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2345: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9031: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9120: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9209: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9298: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9625: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9667: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55f5c9c48130)\\n[serial2console] loaded (0x55f5c9c48130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55f5c9c48130)\\n[serial2tcp] loaded (0x55f5c9c48130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:50:08\\n\\r BIOS CRC passed (97932562)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00002593\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00023660\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8422: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_82"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1897: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1908: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1940: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1951: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1982: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1998: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2041: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2083: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2110: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2142: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2153: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2200: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2211: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2243: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8727: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8816: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8905: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8994: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9277: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9319: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55f711c7a130)\\n[serial2console] loaded (0x55f711c7a130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55f711c7a130)\\n[serial2tcp] loaded (0x55f711c7a130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:50:11\\n\\r BIOS CRC passed (96920b89)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00018663\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00022929\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8118: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_83"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2127: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2138: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2154: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2170: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2181: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2212: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2228: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2239: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2255: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2282: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2302: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2313: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2329: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2340: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2356: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2372: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2383: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2403: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2414: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2430: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2441: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2457: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2473: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2484: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2504: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2515: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9703: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9882: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10061: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10240: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10715: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10757: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bc09771130)\\n[serial2console] loaded (0x55bc09771130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bc09771130)\\n[serial2tcp] loaded (0x55bc09771130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:50:31\\n\\r BIOS CRC passed (5be965c5)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00009886\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00027513\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9080: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_84"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1730: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1757: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1773: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1784: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1804: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1815: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1831: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1874: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1885: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1932: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1959: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1986: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2006: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2033: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2076: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2087: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2107: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2118: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8053: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8084: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8115: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8146: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8313: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8355: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5617d8254130)\\n[serial2console] loaded (0x5617d8254130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5617d8254130)\\n[serial2tcp] loaded (0x5617d8254130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:50:34\\n\\r BIOS CRC passed (63c530b4)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\nBIST-GENERATOR ticks: 00003465\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00003428\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7458: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_85"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1960: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1971: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2003: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2014: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2045: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2061: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2088: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2104: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2135: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2146: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2162: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2189: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2205: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2236: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2247: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2263: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2290: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2306: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2317: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2337: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2348: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9003: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9092: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9181: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9270: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9597: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9639: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a27ddb3130)\\n[serial2console] loaded (0x55a27ddb3130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a27ddb3130)\\n[serial2tcp] loaded (0x55a27ddb3130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:50:54\\n\\r BIOS CRC passed (ef398421)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from BIST-GENERATOR ticks: 00003465\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005750\\nserial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8394: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_86"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1900: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1943: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1954: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1974: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1985: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2001: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2028: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2044: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2075: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2102: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2113: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2145: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2156: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2176: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2187: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2203: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2214: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2230: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2246: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2277: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8699: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8788: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8877: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8966: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9249: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9291: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x56179c032130)\\n[serial2console] loaded (0x56179c032130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x56179c032130)\\n[serial2tcp] loaded (0x56179c032130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:50:55\\n\\r BIOS CRC passed (54b568fb)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from BIST-GENERATOR ticks: 00005776\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00003431\\nserial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8090: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT46V32M16", "name": "test_87"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.14KiB \\t(69.18%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2130: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2157: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2204: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2215: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2231: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2242: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2258: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2285: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2305: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2316: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2332: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2343: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2359: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2375: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2386: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2406: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2417: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2433: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2444: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2460: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2476: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2487: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2507: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2518: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9649: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9828: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10007: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10186: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10661: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:10703: Case values incompletely covered (example pattern 0x11)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_sim__4.cpp Vsim_sim__5.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_sim__4__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp Vsim__Trace__Slow__2.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x558d23dfb130)\\n[serial2console] loaded (0x558d23dfb130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x558d23dfb130)\\n[serial2tcp] loaded (0x558d23dfb130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:51:17\\n\\r BIOS CRC passed (2f81ae61)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t131072KiB 32-bit @ 4MT/s (CL-3 CWL-3)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 353KiB/s\\n\\r Read speed: 240KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00005776\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005749\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9026: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_88"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1666: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1674: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1683: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1692: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1700: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1713: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1721: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1730: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1738: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1747: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1756: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1764: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1777: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1785: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1794: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1802: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1811: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1820: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1828: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1841: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1849: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1858: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1866: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1875: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1892: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1913: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7666: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7697: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7728: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7759: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7981: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8023: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b8cf85c130)\\n[serial2console] loaded (0x55b8cf85c130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b8cf85c130)\\n[serial2tcp] loaded (0x55b8cf85c130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:51:18\\n\\r BIOS CRC passed (0bc19310)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort BIST-GENERATOR ticks: 00004225\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00013704\\nboot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:6952: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_89"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1894: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1902: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1911: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1920: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1928: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1941: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1949: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1958: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1966: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1975: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1984: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1992: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2005: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2013: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2022: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2030: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2039: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2048: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2056: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2069: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2077: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2086: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2094: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2103: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2133: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2141: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8642: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8731: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8820: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8909: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9291: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9333: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5654374e8130)\\n[serial2console] loaded (0x5654374e8130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5654374e8130)\\n[serial2tcp] loaded (0x5654374e8130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:51:38\\n\\r BIOS CRC passed (3a61111c)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00003136\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00022585\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7916: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_90"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1834: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1842: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1851: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1860: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1868: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1881: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1889: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1898: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1906: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1915: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1924: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1932: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1945: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1953: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1962: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1970: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1979: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1988: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1996: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2009: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2017: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2026: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2034: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2043: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2052: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2060: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2081: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8338: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8427: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8516: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8605: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8943: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8985: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bbcbff2130)\\n[serial2console] loaded (0x55bbcbff2130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bbcbff2130)\\n[serial2tcp] loaded (0x55bbcbff2130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:51:41\\n\\r BIOS CRC passed (998725e3)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00017899\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00022119\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7612: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": true, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_91"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2062: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2070: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2079: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2088: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2096: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2109: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2117: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2126: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2134: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2143: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2152: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2160: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2173: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2181: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2190: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2198: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2207: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2216: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2224: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2237: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2245: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2254: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2262: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2271: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2280: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2288: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2301: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2309: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9310: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9489: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9668: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9847: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10377: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10419: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55b9d84ce130)\\n[serial2console] loaded (0x55b9d84ce130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55b9d84ce130)\\n[serial2tcp] loaded (0x55b9d84ce130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:52:00\\n\\r BIOS CRC passed (654202dc)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\nBIST-GENERATOR ticks: 00012392\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00033006\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8572: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_92"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1669: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1677: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1686: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1695: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1703: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1716: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1724: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1733: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1741: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1750: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1759: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1767: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1780: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1788: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1797: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1805: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1814: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1823: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1831: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1844: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1852: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1861: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1869: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1878: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1887: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1895: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1908: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1916: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7668: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7699: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7730: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7761: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7983: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8025: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x564cf52c6130)\\n[serial2console] loaded (0x564cf52c6130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x564cf52c6130)\\n[serial2tcp] loaded (0x564cf52c6130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:52:02\\n\\r BIOS CRC passed (ab4ee172)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ===BIST-GENERATOR ticks: 00002617\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002574\\n===============--\\n\\rBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:6954: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 1, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_93"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1897: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1905: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1914: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1923: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1931: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1944: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1952: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1961: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1969: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1978: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1987: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:1995: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2008: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2016: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2025: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2033: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2042: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2051: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2059: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2072: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2080: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2089: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2097: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2106: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2115: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2123: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2136: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:2144: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8614: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8703: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8792: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:8881: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9263: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:9305: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55bf8c0a3130)\\n[serial2console] loaded (0x55bf8c0a3130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55bf8c0a3130)\\n[serial2tcp] loaded (0x55bf8c0a3130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:52:22\\n\\r BIOS CRC passed (9aee637e)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBIST-GENERATOR ticks: 00002617\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005244\\nBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_01/gateware/sim.v:7888: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 1, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_94"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1837: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1845: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1854: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1863: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1871: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1884: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1892: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1901: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1909: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1918: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1927: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1935: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1948: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1956: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1965: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1973: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1982: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1991: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:1999: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2012: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2020: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2029: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2037: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2046: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2055: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2063: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2076: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2084: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8310: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8399: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8488: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8577: Case values incompletely covered (example pattern 0x5)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8915: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8957: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x5620cf78c130)\\n[serial2console] loaded (0x5620cf78c130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x5620cf78c130)\\n[serial2tcp] loaded (0x5620cf78c130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:52:22\\n\\r BIOS CRC passed (9aee637e)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBIST-GENERATOR ticks: 00005285\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00002574\\nBooting from serial...\\n\\rPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:7584: Verilog $finish\\n\\n'"}, {"config": {"access_pattern": {"pattern_file": "access_pattern.csv"}, "num_checkers": 3, "num_generators": 3, "bist_alternating": false, "sdram_data_width": 32, "sdram_module": "MT48LC16M16", "name": "test_95"}, "output": "b'make: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libcompiler_rt\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\n CC exception.o\\n CC system.o\\n CC id.o\\n CC uart.o\\n CC time.o\\n CC spiflash.o\\n CC i2c.o\\n CC memtest.o\\n CC sim_debug.o\\n AR libbase.a\\n AR libbase-nofloat.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libbase\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\n CC sdram.o\\n CC bist.o\\n AR liblitedram.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitedram\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\n CC udp.o\\n CC mdio.o\\n AR libliteeth.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libliteeth\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\n CC spiflash.o\\n AR liblitespi.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitespi\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Nothing to be done for \\'all\\'.\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/libfatfs\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\n CC sdcard.o\\n CC spisdcard.o\\n AR liblitesdcard.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesdcard\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\n CC sata.o\\n AR liblitesata.a\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/liblitesata\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\n CC isr.o\\n CC boot.o\\n CC cmd_bios.o\\n CC cmd_mem.o\\n CC cmd_boot.o\\n CC cmd_i2c.o\\n CC cmd_spiflash.o\\n CC cmd_litedram.o\\n CC cmd_liteeth.o\\n CC cmd_litesdcard.o\\n CC cmd_litesata.o\\n CC main.o\\n LD bios.elf\\nchmod -x bios.elf\\n OBJCOPY bios.bin\\nchmod -x bios.bin\\npython3 -m litex.soc.software.mkmscimg bios.bin --little\\npython3 -m litex.soc.software.memusage bios.elf /home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios/../include/generated/regions.ld riscv64-unknown-elf\\n\\nROM usage: 22.11KiB \\t(69.10%)\\nRAM usage: 1.63KiB \\t(20.41%)\\n\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/software/bios\\'\\nmake: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\nmkdir -p modules\\nmake -C modules -f /home/travis/litex/litex/build/sim/core/modules/Makefile\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p xgmii_ethernet\\nmake MOD=xgmii_ethernet -C xgmii_ethernet -f /home/travis/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/xgmii_ethernet\\'\\ncp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so\\nmkdir -p ethernet\\nmake MOD=ethernet -C ethernet -f /home/travis/litex/litex/build/sim/core/modules/ethernet/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/ethernet\\'\\ncp ethernet/ethernet.so ethernet.so\\nmkdir -p serial2console\\nmake MOD=serial2console -C serial2console -f /home/travis/litex/litex/build/sim/core/modules/serial2console/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2console\\'\\ncp serial2console/serial2console.so serial2console.so\\nmkdir -p serial2tcp\\nmake MOD=serial2tcp -C serial2tcp -f /home/travis/litex/litex/build/sim/core/modules/serial2tcp/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/serial2tcp\\'\\ncp serial2tcp/serial2tcp.so serial2tcp.so\\nmkdir -p clocker\\nmake MOD=clocker -C clocker -f /home/travis/litex/litex/build/sim/core/modules/clocker/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/clocker\\'\\ncp clocker/clocker.so clocker.so\\nmkdir -p spdeeprom\\nmake MOD=spdeeprom -C spdeeprom -f /home/travis/litex/litex/build/sim/core/modules/spdeeprom/Makefile\\nmake[2]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\nmake[2]: Nothing to be done for \\'all\\'.\\nmake[2]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules/spdeeprom\\'\\ncp spdeeprom/spdeeprom.so spdeeprom.so\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/modules\\'\\nmkdir -p /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/modules.o /home/travis/litex/litex/build/sim/core/modules.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/pads.o /home/travis/litex/litex/build/sim/core/pads.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/sim.o /home/travis/litex/litex/build/sim/core/sim.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/libdylib.o /home/travis/litex/litex/build/sim/core/libdylib.c\\ncc -c -Wall -O0 -ggdb -o /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir/parse.o /home/travis/litex/litex/build/sim/core/parse.c\\nverilator -Wno-fatal -O3 --cc /home/travis/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v --top-module sim --exe \\\\\\n\\t-DPRINTF_COND=0 \\\\\\n\\tsim_init.cpp /home/travis/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \\\\\\n\\t--top-module sim \\\\\\n\\t \\\\\\n\\t-CFLAGS \"-Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core\" \\\\\\n\\t-LDFLAGS \"-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent\" \\\\\\n\\t--trace \\\\\\n\\t \\\\\\n\\t \\\\\\n\\t--unroll-count 256 \\\\\\n\\t--output-split 5000 \\\\\\n\\t--output-split-cfuncs 500 \\\\\\n\\t--output-split-ctrace 500 \\\\\\n\\t \\\\\\n\\t-Wno-BLKANDNBLK \\\\\\n\\t-Wno-WIDTH\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2065: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: Use \"/* verilator lint_off CASEINCOMPLETE */\" and lint_on around source to disable this message.\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2073: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2082: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2091: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2099: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2112: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2120: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2129: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2137: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2146: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2155: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2163: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2176: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2184: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2193: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2201: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2210: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2219: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2227: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2240: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2248: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2257: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2265: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2274: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2283: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2291: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2304: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:2312: Case values incompletely covered (example pattern 0x0)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9256: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9435: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9614: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:9793: Case values incompletely covered (example pattern 0x7)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10323: Case values incompletely covered (example pattern 0x3)\\n%Warning-CASEINCOMPLETE: /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:10365: Case values incompletely covered (example pattern 0x7)\\nmake -j -C /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir -f Vsim.mk Vsim\\nmake[1]: Entering directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o veril.o /home/travis/litex/litex/build/sim/core/veril.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o sim_init.o ../sim_init.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated.o /usr/share/verilator/include/verilated.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_sim__1.cpp Vsim_sim__2.cpp Vsim_sim__3.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_sim__1__Slow.cpp Vsim_sim__2__Slow.cpp Vsim_sim__3__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp\\n/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Trace__1.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp\\ng++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wall -O0 -ggdb -I/home/travis/litex/litex/build/sim/core -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp\\n Archiving Vsim__ALL.a ...\\nar r Vsim__ALL.a Vsim__ALLcls.o Vsim__ALLsup.o\\nar: creating Vsim__ALL.a\\nranlib Vsim__ALL.a\\ng++ veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o Vsim__ALL.a modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -o Vsim -lm -lstdc++ 2>&1 | c++filt\\nmake[1]: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/obj_dir\\'\\nmake: Leaving directory \\'/home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware\\'\\n[clocker] loaded\\n[xgmii_ethernet] loaded (0x55a250160130)\\n[serial2console] loaded (0x55a250160130)\\n[spdeeprom] loaded (addr = 0x0)\\n[ethernet] loaded (0x55a250160130)\\n[serial2tcp] loaded (0x55a250160130)\\n[clocker] sys_clk: freq_hz=1000000, phase_deg=0\\n\\n\\r\\x1b[1m __ _ __ _ __\\x1b[0m\\n\\r\\x1b[1m / / (_) /____ | |/_/\\x1b[0m\\n\\r\\x1b[1m / /__/ / __/ -_)> <\\x1b[0m\\n\\r\\x1b[1m /____/_/\\\\__/\\\\__/_/|_|\\x1b[0m\\n\\r\\x1b[1m Build your hardware, easily!\\x1b[0m\\n\\r\\n\\r (c) Copyright 2012-2020 Enjoy-Digital\\n\\r (c) Copyright 2007-2015 M-Labs\\n\\r\\n\\r BIOS built on Nov 17 2020 16:52:43\\n\\r BIOS CRC passed (af0994bd)\\n\\r\\n\\r Migen git sha1: a5cc037\\n\\r LiteX git sha1: 3bd5d6cc\\n\\r\\n\\r--=============== \\x1b[1mSoC\\x1b[0m ==================--\\n\\r\\x1b[1mCPU\\x1b[0m:\\t\\tVexRiscv @ 1MHz\\n\\r\\x1b[1mBUS\\x1b[0m:\\t\\tWISHBONE 32-bit @ 4GiB\\n\\r\\x1b[1mCSR\\x1b[0m:\\t\\t32-bit data\\n\\r\\x1b[1mROM\\x1b[0m:\\t\\t32KiB\\n\\r\\x1b[1mSRAM\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mL2\\x1b[0m:\\t\\t8KiB\\n\\r\\x1b[1mSDRAM\\x1b[0m:\\t\\t65536KiB 32-bit @ 1MT/s (CL-2 CWL-2)\\n\\r\\n\\r--========== \\x1b[1mInitialization\\x1b[0m ============--\\n\\rInitializing SDRAM @0x40000000...\\n\\rSwitching SDRAM to software control.\\n\\rSwitching SDRAM to hardware control.\\n\\rMemtest at 0x40000000 (8KiB)...\\n\\r Write: 0x40000000-0x40000000 0B \\r Write: 0x40000000-0x40002000 8KiB \\r\\n\\r Read: 0x40000000-0x40000000 0B \\r Read: 0x40000000-0x40002000 8KiB \\r\\n\\rMemtest OK\\n\\rMemspeed at 0x40000000 (8KiB)...\\n\\r Write speed: 354KiB/s\\n\\r Read speed: 227KiB/s\\n\\r\\n\\r--============== \\x1b[1mBoot\\x1b[0m ==================--\\n\\rBooting from serial...\\n\\rBIST-GENERATOR ticks: 00005285\\nBIST-CHECKER errors: 00000000\\nBIST-CHECKER ticks: 00005256\\nPress Q or ESC to abort boot completely.\\n\\rsL5DdSMmkekro\\n- /home/travis/build/enjoy-digital/litedram/test/build/worker_00/gateware/sim.v:8518: Verilog $finish\\n\\n'"}] \ No newline at end of file diff --git a/index.html b/index.html index d683d3a..ed160be 100644 --- a/index.html +++ b/index.html @@ -400,7 +400,7 @@ footer { 3 3 20 clk - 148 clk + 137 clk 40 @@ -448,7 +448,7 @@ footer { 3 3 20 clk - 116 clk + 126 clk 48 @@ -887,9 +887,9 @@ footer { 1 1024 access_pattern.csv - 184.4 Mbps - 57.1 Mbps - 6.0 % + 184.9 Mbps + 57.0 Mbps + 6.1 % 1.9 % @@ -1159,10 +1159,10 @@ footer { 1 1 1024.0 - 2.0 Gbps - 777.4 Mbps - 16.8 % - 6.4 % + 1.9 Gbps + 790.7 Mbps + 16.2 % + 6.5 % 31 @@ -1190,9 +1190,9 @@ footer { 1 1024.0 1.9 Gbps - 511.3 Mbps - 15.8 % - 4.2 % + 521.2 Mbps + 15.6 % + 4.3 % 39 @@ -1264,9 +1264,9 @@ footer { 3 3 1024.0 - 11.0 Gbps + 9.8 Gbps 9.3 Gbps - 91.9 % + 82.1 % 78.4 % @@ -1485,9 +1485,9 @@ footer { 1 1024.0 3.7 Gbps - 651.6 Mbps + 659.8 Mbps 31.4 % - 5.3 % + 5.4 % 30 @@ -1515,8 +1515,8 @@ footer { 1 1024.0 1.6 Gbps - 451.9 Mbps - 13.1 % + 453.4 Mbps + 13.4 % 3.7 % @@ -1632,10 +1632,10 @@ footer { LiteDRAM is a part of Litex.
Generated using - test/run_benchmarks.py, + test/run_benchmarks.py, revision - 1117068, - 2020-11-12 19:01:20. + b625234, + 2020-11-17 16:52:55.