From fef530366aae79c9cb5c4ef7a9ae13a09f9c25f4 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 13 Jun 2019 09:15:09 +0200
Subject: [PATCH] test: clean test_downconverter/test_upconverter (thanks sb0)

---
 test/test_downconverter.py | 17 +++++++----------
 test/test_upconverter.py   | 17 +++++++----------
 2 files changed, 14 insertions(+), 20 deletions(-)

diff --git a/test/test_downconverter.py b/test/test_downconverter.py
index 7d76332..6b2578c 100755
--- a/test/test_downconverter.py
+++ b/test/test_downconverter.py
@@ -80,14 +80,11 @@ def main_generator(write_port, read_port):
 class TestDownConverter(unittest.TestCase):
     def test(self):
         dut = DUT()
-        generators = {
-            "sys" : [
-                main_generator(dut.write_user_port, dut.read_user_port),
-                read_handler(dut.read_user_port),
-                dut.memory.write_handler(dut.write_crossbar_port),
-                dut.memory.read_handler(dut.read_crossbar_port)
-            ]
-        }
-        clocks = {"sys": 10}
-        run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
+        generators = [
+            main_generator(dut.write_user_port, dut.read_user_port),
+            read_handler(dut.read_user_port),
+            dut.memory.write_handler(dut.write_crossbar_port),
+            dut.memory.read_handler(dut.read_crossbar_port)
+        ]
+        run_simulation(dut, generators)
         self.assertEqual(write_data, read_data)
diff --git a/test/test_upconverter.py b/test/test_upconverter.py
index baa5d1f..0555f6d 100755
--- a/test/test_upconverter.py
+++ b/test/test_upconverter.py
@@ -83,14 +83,11 @@ def main_generator(write_port, read_port):
 class TestUpConverter(unittest.TestCase):
     def test(self):
         dut = DUT()
-        generators = {
-            "sys" :   [
-                main_generator(dut.write_user_port, dut.read_user_port),
-                read_handler(dut.read_user_port),
-                dut.memory.write_handler(dut.write_crossbar_port),
-                dut.memory.read_handler(dut.read_crossbar_port)
-            ]
-        }
-        clocks = {"sys": 10}
-        run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
+        generators = [
+            main_generator(dut.write_user_port, dut.read_user_port),
+            read_handler(dut.read_user_port),
+            dut.memory.write_handler(dut.write_crossbar_port),
+            dut.memory.read_handler(dut.read_crossbar_port)
+        ]
+        run_simulation(dut, generators)
         self.assertEqual(write_data, read_data)