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litedram
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27 Commits

Author SHA1 Message Date
Florent Kermarrec 39c0b0356c bench/uartbone: Update with LiteX change. 2023-07-20 15:44:18 +02:00
Florent Kermarrec 745f2a060a bench/targets: Use full imports. 2022-05-02 13:07:29 +02:00
Florent Kermarrec 5f722a1513 bench/test: Avoid use of ident_version (should fix CI). 2022-02-15 17:33:31 +01:00
Florent Kermarrec 5a4ed3d204 bench/arty/kc705: Use PHYPadsReducer to easily test various DFI sizes. 2021-07-09 17:58:40 +02:00
Florent Kermarrec e90aa5a4d5 bench/targets: Minor CRG cleanups. 2021-06-29 12:36:02 +02:00
Florent Kermarrec 6256031d51 bench: Update build directories and add rst in CRG (triggered on CPU reboot). 2021-04-22 14:57:13 +02:00
Florent Kermarrec c2a779df46 bench: Update test targets (add_csr no longer required). 2021-04-19 13:40:17 +02:00
Florent Kermarrec 5cd192a708 bench: Remove soc_sdram import (No longer useful and deprecated). 2021-03-30 08:49:54 +02:00
Florent Kermarrec df5f555842 bench: Update with recent changes. 2021-03-12 10:25:11 +01:00
Florent Kermarrec a87c468afa bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale. 2020-12-10 19:06:19 +01:00
Florent Kermarrec efb1975d00 bench/arty: add missing eth clock. 2020-12-10 13:43:31 +01:00
Florent Kermarrec 75f87538a5 bench: use common load_bios function. 2020-12-10 11:21:21 +01:00
Florent Kermarrec ea63480253 bench/targets: add identifier. 2020-12-10 11:12:45 +01:00
Florent Kermarrec c472499131 bench/targets: add optional analyzer on all test targets. 2020-12-10 08:44:35 +01:00
Florent Kermarrec 5cfdf77654 bench/targets: simplify BIST integration using new add_sdram with_bist parameter. 2020-11-06 10:34:26 +01:00
Florent Kermarrec a95c6883cc bench/targets: uniformize. 2020-10-29 18:58:37 +01:00
Florent Kermarrec 06544c6547 bench: uniformize targets with 125MHz clock and Etherbone. 2020-09-24 13:03:07 +02:00
Florent Kermarrec 7eeea34c4e bench: use 115200bauds UART on all targets (fast enough and simplify switch betwen targets). 2020-09-14 10:05:55 +02:00
Florent Kermarrec 7d0dac78c5 bench/kcu105: add a second pll to reduce frequency steps. 2020-08-28 19:03:44 +02:00
Florent Kermarrec 1fb78fa558 bench: cleanup, do more testing on 7-series. 2020-08-28 17:57:59 +02:00
Florent Kermarrec 248c5de517 bench: switch to UARTBone to simplify (and to allow testing boards without ethernet capability) and improve test. 2020-08-28 03:47:49 +02:00
Florent Kermarrec d3502e6a9b bench: add common.py with common bench test code. 2020-08-27 19:05:05 +02:00
Florent Kermarrec 2e3e19e9d4 bench: simplify/improve, working on arty/genesys2. 2020-08-27 18:41:54 +02:00
Florent Kermarrec 9995c0fefb bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. 
This simplifies software development.
 2020-08-24 18:40:54 +02:00
Florent Kermarrec ac825e5112 add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
Florent Kermarrec 94241d0583 bench: use new platform.request_all on LedChaser. 2020-08-06 20:03:03 +02:00
Florent Kermarrec 37fb44f33e add bench directory with a first bench on arty board. 
The aim is to create an automated hardware bench, control is done over Etherbone
(but could also be done over UARTBone, PCIe, USB, etc...) and various frequencies
are tested and BIOS logged.

It would also be useful to be able to recompile/reload BIOS in this bench to easily
test software changes and verify it works with various frequencies.

Can be tested with:
./arty.py --build --load
lxserver --udp
./arty.py --test
Dump Main PLL...
ClkReg1:
  low_time:  8
  high_time: 8
  reserved:  1
  phase_mux: 0
Reconfig Main PLL to 133.33333333333331MHz...
Measuring sys_clk...
sys_clk: 133.72MHz
Reset SoC and get BIOS log...

        __
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Aug  6 2020 18:49:15
 BIOS CRC passed (44c8f057)

 Migen git sha1: 7bc4eb1
 LiteX git sha1: 188e6f57

--=============== SoC ==================--
CPU:       VexRiscv @ 100MHz
BUS:       WISHBONE 32-bit @ 4GiB
CSR:       32-bit data
ROM:       32KiB
SRAM:      8KiB
L2:        8KiB
MAIN-RAM:  262144KiB

--========== Initialization ============--
Initializing DRAM @0x40000000...
SDRAM now under software control
SDRAM now under software control
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |00000000000000000000000000000000| delays: -
m0, b03: |00000000000000000000000000000000| delays: -
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
m0, b08: |00000000000000000000000000000000| delays: -
m0, b09: |11111111111000000000000000000000| delays: 05+-05
m0, b10: |00000000000111111111110000000000| delays: 16+-05
m0, b11: |00000000000000000000000111111111| delays: 27+-04
m0, b12: |00000000000000000000000000000000| delays: -
m0, b13: |00000000000000000000000000000000| delays: -
m0, b14: |00000000000000000000000000000000| delays: -
m0, b15: |00000000000000000000000000000000| delays: -
best: m0, b09 delays: 05+-05
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |00000000000000000000000000000000| delays: -
m1, b03: |00000000000000000000000000000000| delays: -
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
m1, b08: |00000000000000000000000000000000| delays: -
m1, b09: |11111111111000000000000000000000| delays: 05+-05
m1, b10: |00000000000011111111111000000000| delays: 17+-05
m1, b11: |00000000000000000000000011111111| delays: 28+-04
m1, b12: |00000000000000000000000000000000| delays: -
m1, b13: |00000000000000000000000000000000| delays: -
m1, b14: |00000000000000000000000000000000| delays: -
m1, b15: |00000000000000000000000000000000| delays: -
best: m1, b09 delays: 05+-05
SDRAM now under hardware control
Memtest at 0x40000000...
[########################################]
[########################################]
Memtest OK
Memspeed at 0x40000000...
Writes: 212 Mbps
Reads:  188 Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--


litex> Reconfig Main PLL to 114.28571428571428MHz...
 2020-08-06 19:05:20 +02:00