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litedram
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3 Commits

Author SHA1 Message Date
Florent Kermarrec e0e204a514 litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 
It's more interesting in some design to access the UART through a FIFO like
interface than through RS232.
 2021-09-16 17:01:00 +02:00
Florent Kermarrec a11d1b870d litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY. 
By specifying FPGA device in .yml files for configs requiring  it.
 2021-07-02 09:15:42 +02:00
Florent Kermarrec 317072a198 litedram_gen: Add initial SDRAM support (with ULX3S example). 2021-07-02 09:01:31 +02:00