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12 Commits

Author SHA1 Message Date
Michal Sieron a912a88081 Make tests safe to run in parallel 
For example using pytest-parallel you can greatly reduce time it takes
to run all tests.

```
$ pytest --workers auto test
```

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 21:49:50 +01:00
Florent Kermarrec c770dd62ed test/test_lpddr5: Add tINIT2 as allowed warning. 2022-10-25 08:58:20 +02:00
Alessandro Comodi 50ba27eb4c lpddr5: tests: add additional initial tCK delay for bitslip 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Alessandro Comodi ab130e170a lpddr5: add write leveling support 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 43aef6255e phy/lpddr5: add Verilator tests 2021-10-26 12:22:30 +02:00
Alessandro Comodi abc77f367c lpddr5: wck sync: fix syncing and adjusted unit tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Alessandro Comodi c4273146c1 lpddr5: wck sync: adapt tests as now wck sync is required 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 8c10f1405b phy/lpddr5: delay WCK sync FSM transition by 1 cycle 
With fixed serialization logic WCK sync can be now started later
which avoids the need for special logic when tWCKENL=0.
 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 32a56ffe28 phy/lpddr5: fix command serialization 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 4e974738d1 phy/lpddr5: fix column address encoding/decoding 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 2671508a11 phy/lpddr5: add simulation SoC 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 7cdf0e11ca phy/lpddr5: add unit tests 2021-10-26 12:22:30 +02:00