478b8c1df3
phy/kusddrphy: integrate BitSlip module (in fabric) and instanciate ISERDESE3
2017-02-10 12:51:30 +01:00
c94b1e7d0a
phy: cleanup instances indentation
2017-02-10 10:06:31 +01:00
062177502b
phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3)
2017-02-10 08:59:13 +01:00
1430cb3d49
phy: add initial Kintex Ultrascale PHY (incomplete)
...
Input deserializer still missing, need to implement bitslip in logic and use new fifo interface.
Others primitives should be fine.
2017-02-09 13:25:45 +01:00
4f51524921
frontend/bist: rename err_count to errors
2017-01-17 14:30:23 +01:00
e7fe539c73
frontend/bist: remove LiteDRAMBISTCheckerScope.
...
Checker should not be used to investigate errors but only to verify that is already validated still works. (ie we don't want to be able to understand what is going on, just to know if it's working or not). To understand what is going on we will look at signals with LiteScope and eventually trigger on err_count from checker.
2017-01-17 13:48:03 +01:00
c142db3966
Creating a utility module for easily scoping the LiteDRAMBISTChecker module.
2016-12-19 17:49:24 +01:00
0f151c5499
frontend/bist: small cleanup
2016-12-17 19:22:56 +01:00
a613c49783
frontend/bist: cleanup the way we expose signals for debugging
2016-12-17 19:04:58 +01:00
e21b45b608
Merge remote-tracking branch 'upstream/master' into bist
2016-12-17 18:15:59 +01:00
bc75d4f3d5
bist: Reworking as suggested by Florent.
2016-12-17 17:49:47 +01:00
5909e5d76e
frontend/bist: refactor(simplify) LiteDRAMBISTChecker
2016-12-17 17:08:50 +01:00
381789c84d
frontend/bist: refactor(simplify) LiteDRAMBISTGenerator, use start instead of shoot
2016-12-17 16:38:59 +01:00
70a333628b
dma: Adding some documentation.
2016-12-17 14:09:50 +01:00
fcc1d5059e
bist: Improving documentation a bit.
2016-12-17 14:09:50 +01:00
f1ad8991a4
bist: Working on improving the names of things.
2016-12-17 14:09:50 +01:00
8ff2f8779b
bist: Adding "halt on error" functionality.
...
Also include ability to see address of error and expected verse actual
data values.
Extend the test bench to test this functionality.
2016-12-17 14:09:50 +01:00
c0b8d1a714
bist: Adding some documentation.
...
(Plus small formatting cleanup.)
2016-12-17 14:09:50 +01:00
dc14a98bf4
bist: s/shoot/start/
2016-12-17 14:09:50 +01:00
6ae11fa5c8
bist: Make reset write to activate like shoot.
2016-12-17 14:09:50 +01:00
85e4b65550
bist: Small formatting change.
2016-12-17 14:09:50 +01:00
e901305e56
bist: Done only goes high after bist runs.
2016-12-17 14:09:50 +01:00
f57dfad6a4
frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter
2016-12-15 19:07:43 +01:00
bd40268961
frontend/dma: add fifo_buffered parameter
2016-10-28 09:48:25 +02:00
6e3f5e4d98
frontend: add reverse parameter to converters
2016-06-21 17:29:12 +02:00
2ed7212701
frontend/crossbar: fix sign on adr_shift
2016-06-20 21:40:32 +02:00
ad8ca86e13
frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly
...
still some corner cases to manage
2016-06-15 23:57:16 +02:00
5823373243
frontend: introduce mode on ports: write, read or both
2016-06-15 17:51:46 +02:00
b0382e8776
frontend/crossbar: add clock domain crossing and data width convertion to get_port
2016-06-13 14:41:57 +02:00
ed997f1cfe
core: fix refresh (bug was reducing controller throughput by 2)
2016-06-13 13:11:41 +02:00
870638fc50
frontend/adaptation: small optimization on LiteDRAMPortUpConverter (still to be refactored)
2016-06-12 16:53:44 +02:00
edbebfa8a2
frontend/adaptation: add workaround on LiteDRAMPortUpConverter to increase throughput on reads (to be fixed since only working for our actual usecase)
2016-06-10 22:07:53 +02:00
66907f1468
frontend/adaptation: expose LiteDRAMPortDownConverter, LiteDRAMPortUpConverter
2016-06-10 19:13:12 +02:00
afd2e441eb
frontend/adaptation: fix some comments
2016-06-08 17:32:08 +02:00
25c5a8aaf5
frontend/adaptation: adapt fifo depths
2016-06-02 22:35:27 +02:00
0faee6639d
frontend/bist: add random parameter on generator/checker to ease debug
2016-06-02 18:35:45 +02:00
a5ff573046
frontend/bist: rename generator/checker to core
2016-06-02 09:27:46 +02:00
41364dd0b1
frontend/bist: fix cd on LiteDRAMBISTChecker, bist_async_tb now working
2016-05-29 16:00:35 +02:00
cb69561137
phy/model: add we_granularity parameter as simulator bug workaround (to be removed)
2016-05-28 13:02:40 +02:00
8ee2992e5b
frontend/bist: simplify and use incrementing addressing
2016-05-26 12:04:41 +02:00
b3a11fb669
frontend: move port adaptation modules to adaptation.py and do adaptation manually (and not in get_port)
2016-05-26 11:03:55 +02:00
32a6e25021
test: add upconverter_tb and some fixes
2016-05-24 21:14:49 +02:00
de61cefb58
test: add downconverter_tb and some fixes
2016-05-24 20:48:26 +02:00
777d907da1
frontend/crossbar: fill LiteDRAMUpConverter (incomplete and to be tested)
2016-05-24 08:49:53 +02:00
f70e28beac
frontend/crossbar: fill LiteDRAMDownConverter (to be tested)
2016-05-24 08:34:14 +02:00
b76f7e6e07
frontend/crossbar: add skeleton/descroption for port downconverters/upconverters
2016-05-24 06:56:58 +02:00
6f10314d43
frontend/bist: remove cd parameter (already available with dram_port.cd)
2016-05-23 17:37:30 +02:00
b258c9a913
test: add bist_async_tb and some fixes
2016-05-23 17:20:42 +02:00
cb42ea510d
frontend/bist: LiteDRAMBISTChecker can now be asynchronous
2016-05-23 14:26:53 +02:00
cb324ea47c
frontend/bist: LiteDRAMBISTGenerator can now be asynchronous
2016-05-23 14:17:22 +02:00
a016a820b5
common/LiteDRAMPort: add defaut cd value
2016-05-18 15:49:44 +02:00
8d066caea9
common: use cmd/wdata/rdata stream on LiteDRAMPort
2016-05-13 15:46:15 +02:00
30bacfeb1b
frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests)
2016-05-13 15:27:12 +02:00
19a0bd59d2
frontend/dma: use stream.SyncFIFO
2016-05-13 13:35:59 +02:00
8b98dd3c8a
frontend: simplify wdata/wdata_we on user side (implement the mux in the crossbar)
2016-05-12 15:34:39 +02:00
9d2c8bf1cf
frontend: remove geom/timing parameters from LiteDRAMPort since this prevent providing async or arbitraty length port easily
2016-05-09 12:07:06 +02:00
68e4b9322c
phy/s6ddrphy: fix
2016-05-04 01:10:44 +02:00
bb67fdba57
core/perf: fix
2016-05-04 00:26:32 +02:00
37c9d6dd46
frontend/bist: fix missing AutoCSR
2016-05-04 00:26:24 +02:00
a40b0f760c
test/bist_tb: cleanup and add error check
2016-05-03 22:22:11 +02:00
812d7dd7f0
frontend/bist: reword bist, add simulation, seems to work but need more testing
2016-05-03 19:24:33 +02:00
4c1b97b465
core/refresher: remove req/ack signal and use stream
2016-05-03 17:45:57 +02:00
3d9ea833dd
frontend/crossbar: continue cleanup/simplify
2016-05-03 17:24:11 +02:00
2ef8879661
frontend/crossbar: replace rr by arbiter
2016-05-03 17:14:03 +02:00
2709efa4a7
frontend/crossbar: remove controller_selected (no longer needed)
2016-05-03 17:11:34 +02:00
e712a9d565
changes names on cmd_layout and data_layout
2016-05-03 17:02:59 +02:00
6e15824161
core: replace lasmic with interface and some cleanup
2016-05-03 16:55:54 +02:00
8c0e732c24
core: use a single structure to pass settings / simplify
2016-05-02 21:38:18 +02:00
7ce42d5324
bankmachine: rename fifo to cmd_buffer and allow depth < 2 (will be used to reduce logic when performance is not the priority)
2016-05-02 20:50:55 +02:00
8d29e5a905
bank_machine: cleanup/pep8
2016-05-02 16:06:37 +02:00
d3ff63b978
multiplexer: cleanup/pep8
2016-05-02 15:57:39 +02:00
3177f7964f
multiplexer: rewrite/simplify CommandChooser
2016-05-02 15:37:12 +02:00
fb98d12241
only use positive logic in the controller(cas/ras/we) and use Record/stream.Endpoint for command requests
2016-05-02 12:18:56 +02:00
cbe9748fa1
continue cleanup
2016-05-02 09:48:17 +02:00
f37fc3d854
common: split Interface in InternalInterface/UserInterface
2016-05-02 09:20:12 +02:00
52a0f4e617
stb/req_ack becomes valid/ready + others small cleanup
2016-05-02 09:13:09 +02:00
19e84975f6
core/bankmachine: small cleanup
2016-05-01 12:43:33 +02:00
82e42bb500
core/perf: remove _ on CSRs
2016-05-01 12:27:50 +02:00
b874500b77
core/refresher: simplify/cleanup
2016-05-01 12:15:49 +02:00
400de46980
frotend/crossbar: make parameters public
2016-05-01 12:08:03 +02:00
cb32238b01
core/bankmachine: replace fifo with stream.SyncFIFO
2016-05-01 12:00:48 +02:00
ca9d33da83
phy: add small description on a7ddrphy/k7ddrphy
2016-05-01 10:21:22 +02:00
802227bbcf
model: move in phy
2016-05-01 10:20:05 +02:00
3cf8b07b8a
core: add with_refresh parameter (to be able to desactivate refresh during simulation)
2016-04-29 23:01:55 +02:00
9d30fb4111
frontend: rename tester to bist
2016-04-29 19:28:41 +02:00
1dac3fb7ba
common: remove use of namedtuple (to improve readibility)
2016-04-29 19:22:06 +02:00
297c85d6cf
move SDRAM modules in modules.py and others settings in common.py
2016-04-29 19:08:56 +02:00
3dab76514a
frontend/crossbar: get_master --> get_port
2016-04-29 17:42:32 +02:00
c8d2850e8c
frontend: dma_lasmi --> dma, wishbone2lasmi --> bridge
2016-04-29 17:42:07 +02:00
97fb293109
core/controller: aerate code
2016-04-29 17:28:58 +02:00
997c1ce707
rename bus to common
2016-04-29 17:15:06 +02:00
077043e310
frontend/crossbar: remove support of multiple controller (too complex and never used)
2016-04-29 17:06:43 +02:00
47f2859091
move crossbar to frontend, adapt core
2016-04-29 16:48:35 +02:00
41c76899d5
rename lasmicon to core
2016-04-29 16:35:24 +02:00
0051f368cc
remove minicon
2016-04-29 16:27:12 +02:00
319ecdc986
phy/a7ddrphy: remove uneeded wrlevel registers
2016-04-29 15:56:17 +02:00
bf291f523a
settings: add MT41K128M16 (Arty) and MT41K256M16 (Nexys video)
2016-04-29 08:11:37 +02:00
6ef6e2f388
phy: add Artix7 a7ddrphy (Arty, Nexys Video)
2016-04-29 08:08:59 +02:00
d48c298363
init from LiteX/MiSoC
2016-04-29 07:44:30 +02:00
0ef987dab1
bankmachine: some changes and first tests
2015-09-27 23:42:05 +02:00
7732ff27a6
update code, start bankmachine refactoring and remove old code (will be rewritten)
2015-09-15 10:22:39 +02:00
90595646f0
core / bankmachine / multiplexer skeleton
2015-02-22 21:59:48 +01:00
2ea2cb1e78
import code from MiSoC
2015-02-22 18:33:14 +01:00
230bad1b23
init structure
2015-02-22 18:25:36 +01:00
Florent Kermarrec
Tim 'mithro' Ansell