e1598ceee8
phy/s7ddrphy: fix BL8 assert
2018-09-04 09:34:10 +02:00
ebba39d928
README: update
2018-09-03 14:18:35 +02:00
e528e92b9b
phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY)
2018-09-03 14:06:04 +02:00
6017e7a763
phy/s7ddrphy: fix dqs_sys_latency for DDR2
2018-09-03 12:21:04 +02:00
7b427391bd
phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions.
...
The real restrictions are:
- dat_phase = sys_latency*nphases - cas_latency (at least for writes, for read we can compensate that with bitslip)
- dat_phase != cmd_phase.
2018-09-03 11:15:37 +02:00
614861891e
phy/s7ddrphy: use dict in get_cl_cw function
2018-09-03 10:18:54 +02:00
5e4dca9a7b
add examples with standalone cores for arty and genesys2
2018-08-31 23:20:47 +02:00
dce4edee97
README: update
2018-08-31 08:25:05 +02:00
f6797a16bb
test/test_axi: add burst wrap test and fix code
2018-08-29 18:47:40 +02:00
47988d8cd3
frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification.
2018-08-29 18:08:50 +02:00
6cc42c63c5
frontend/axi: add wrap burst support
2018-08-29 17:53:26 +02:00
9c729ae7b5
core: replace adr with addr on native interface (closer to AXI and allow some simplifications)
2018-08-29 17:06:03 +02:00
050670829a
core/controller: remove simulation workaround
2018-08-29 16:48:06 +02:00
bc8a9cef7d
README: update
2018-08-29 16:34:53 +02:00
6f7ae8496b
frontend/axi: increase default depth of buffers to improve performance
2018-08-29 16:28:07 +02:00
ed7eef12d4
phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted)
2018-08-29 14:15:31 +02:00
c37d3af5b5
frontend/bist: only keep random datas (we can generate random addresses with control)
2018-08-28 22:54:23 +02:00
b1e734b2ac
frontend/bist: only use cdc on registers if needed (ie not in sys clock domain)
2018-08-28 18:59:56 +02:00
92c8513598
frontend/axi: add buffer to accept command before converting burst to beats
2018-08-28 14:09:59 +02:00
c15c47497a
test/test_axi: split reads/writes generators
2018-08-28 14:09:12 +02:00
95cb7cdba5
test: rename read/write generators to handlers
2018-08-28 13:40:50 +02:00
d5d673708d
frontend/axi: fix read id
2018-08-28 13:39:29 +02:00
10229d1e7d
test/test_axi: improve test_axi2native
2018-08-28 13:39:11 +02:00
295f016fd2
frontend/axi: add features/limitations
2018-08-28 12:39:49 +02:00
6a46ea3052
test/test_bist: add generator test, remove async test
2018-08-28 11:50:11 +02:00
7677a853f1
core/bankmachine: expose cmd_buffer_buffered param and small cleanup
2018-08-28 11:19:48 +02:00
7a5ac75e22
test/test_axi: improve test_axi2native
2018-08-27 18:39:36 +02:00
d53832d55a
frontend/axi: split LiteDRAMAXI2Native (write path and read path)
2018-08-27 18:39:09 +02:00
c846b8b1c7
frontend/axi: add burst support (fixed/incr)
2018-08-27 16:21:12 +02:00
3fa77c8417
phy/s6ddrphy: use cwl only for DDR3
2018-08-27 14:06:32 +02:00
d9b5bb7247
frontend/bist: support axi with addressing in bytes
2018-08-27 12:42:30 +02:00
137061734b
frontend/axi: addressing in bytes not internal dwords
2018-08-27 11:05:37 +02:00
06f841dc2a
sdram_init: compute write recovery cycles (we were using max value)
...
Also replace sdram_phy_settings with phy_settings
2018-08-22 14:44:46 +02:00
53c75f50c8
phy/s7ddrphy: add dqs preamble/postamble
2018-08-22 12:32:19 +02:00
1c083ea9df
sdram_init: split init_sequence generation and header geneneration and add .py header genration
2018-08-21 18:14:19 +02:00
d7d60cf30b
Merge branch 'master' of http://github.com/enjoy-digital/litedram
2018-08-21 15:58:30 +02:00
ae6f10a7e1
sdram_init: use 60ohm as rtt_wr default value
...
Seems the best for point to point according to tn4113_ddr3_point_to_point_design
2018-08-21 15:58:07 +02:00
cd330b4b44
Merge pull request #28 from AlphamaxMedia/refactor-master
...
i think there's a missing "self" in the params
2018-08-21 15:22:50 +02:00
522cbc97a1
frontend: add AXI support for dma and bist
2018-08-21 14:49:10 +02:00
57157345cf
frontend: add initial AXI support
2018-08-21 13:39:46 +02:00
97349bc11b
frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native
2018-08-21 13:27:49 +02:00
2b20c11e2d
add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility
...
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
2018-08-21 13:21:04 +02:00
818c6785f0
update module settings to reflect latest changes
2018-08-21 17:59:54 +08:00
c9b8db5dc9
i think there's a missing "self" in the params
2018-08-21 17:28:42 +08:00
0b6e21ab6d
improve ddr3 electrical settings
2018-08-21 10:45:42 +02:00
697eaafc4c
add board tuning parameters
2018-08-21 09:20:21 +02:00
9a57c4e88c
phy/s7ddrphy: add DDR3-800 timings
2018-08-21 09:02:57 +02:00
9401b92c71
move sdram_init to litedram
2018-08-20 15:37:39 +02:00
209dc0d781
frontend/bist: add dynamic random data and addressing
2018-08-17 13:49:27 +02:00
b13962c7bd
core/multiplexer: fix 1:1
2018-08-16 15:48:26 +02:00
Florent Kermarrec
bunnie