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1483 Commits

Author SHA1 Message Date
Hans Baier f1293eae1e
Avalon frontend for LiteDRAM (#337) 
Add initial Avalon MM frontend + tests.
 2023-05-23 14:52:05 +02:00
Florent Kermarrec d7df59560e setup.py: Prepare for 2023.04. 2023-05-07 20:47:47 +02:00
enjoy-digital e452da7a00
Merge pull request #330 from timkpaine/tkp/ci 
add manifest, uplift setup.py to pass twine checks
 2023-04-11 17:01:51 +02:00
Tim Paine ad00237fa2 fix typo in ci 2023-04-07 19:08:35 -04:00
Tim Paine 81203855a6 move up version 2023-04-07 19:06:45 -04:00
Tim Paine d7886c5fc5 add manifest, uplift setup.py to pass twine checks 2023-04-07 18:59:35 -04:00
enjoy-digital 6c8df7cc7b
Merge pull request #326 from trabucayre/gw2ddrphy_fix_warnings 
phy/gw2ddrphy: supressing warnings about unconnected and bit length.
 2023-02-08 19:12:01 +01:00
Gwenhael Goavec-Merou 895b653a96 phy/gw2ddrphy: supressing warnings about unconnected and bit length. 2023-02-08 18:26:54 +01:00
enjoy-digital 455305a3ed
Merge pull request #322 from antmicro/msieron/make-tests-parallel-safe 
Make tests safe to run in parallel
 2023-01-31 08:25:18 +01:00
Florent Kermarrec f94366c769 ci: Add help2man install for verilator compilation. 2023-01-20 19:14:17 +01:00
Florent Kermarrec 18f00151ed ci: Specify verilator sha1 (Build broken with recent versions). 2023-01-19 10:01:38 +01:00
Florent Kermarrec d95c1fc583 frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade). 2023-01-16 11:21:47 +01:00
Michal Sieron a912a88081 Make tests safe to run in parallel 
For example using pytest-parallel you can greatly reduce time it takes
to run all tests.

```
$ pytest --workers auto test
```

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 21:49:50 +01:00
enjoy-digital b749e10970
Merge pull request #321 from antmicro/msieron/sdram-hw-test 
frontend/bist: replicate LFSR output to fill the DRAM port
 2023-01-11 19:10:23 +01:00
Michal Sieron dad2c972f7 test/common: fix expected data for test_bist.py 
Expected data needs to be replicated to fill given data_width.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 17:13:52 +01:00
Michal Sieron 73c3ec6b68 frontend/bist: make LFSR output comb 
Otherwise first output after reset is 0.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Michal Sieron f466c5f1db frontend/bist: replicate LFSR output to fill DRAM port 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Michal Sieron 89581c1da7 gen: increase ROM size 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Florent Kermarrec 69b401dea1 test/test_init: Update. 2023-01-10 14:45:27 +01:00
enjoy-digital d17b021aa2
Merge pull request #320 from antmicro/msieron/sdram-spd 
init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`
 2023-01-10 09:39:12 +01:00
Michal Sieron 8fa325310a init: define SDRAM_PHY_SUPPORTED_MEMORY 
To use as a default value when one can't read SDRAM size from the SPD.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:03:09 +01:00
Michal Sieron 4c9f184566 init: define SDRAM_PHY_[DDR3|DDR4|...] 
Will allow to ifdef code specific to some memory types like SPD reads.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:03:09 +01:00
enjoy-digital 8339f54322
Merge pull request #319 from antmicro/msieron/fix-bist-errors 
frontend/bist: properly signal finished writes
 2023-01-05 22:21:23 +01:00
Michal Sieron f45ca410ad frontend/bist: properly signal finished writes 
Without it, software was resetting the generator too early and wrong
data was being written to the RAM.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-04 14:00:59 +01:00
Florent Kermarrec 3b2bcf91ed ci: Switch to ubuntu 22.04 and increase similarities with LiteX's CI. 2022-12-09 11:06:58 +01:00
Florent Kermarrec 6b00d1adce ci: Install RISC-V GCC with litex_setup.py. 2022-12-08 21:57:50 +01:00
Florent Kermarrec 379db85fc7 bench: Update with LiteX/LiteX-Boards changes. 2022-12-08 10:29:43 +01:00
enjoy-digital 1f1ab2d3ea
Merge pull request #314 from antmicro/msieron/fix-ddr4-sim 
Fix DFITimingsChecker for DDR4 simulation
 2022-11-18 12:47:13 +01:00
Michal Sieron f25604c153 Fix DFITimingsChecker for DDR4 simulation 
In case of DDR4 tRFC and tREFI timings are actually dictionaries with
timings specific for the chosen refresh mode.

Right now, it is impossible to simulate DDR4, because an exception
happens in `DFITimingsChecker.prepare_timings` method when indexing
`val` variable.

This is due to the fact, that in `DFITimingsChecker.__init__` we request
timing values from the module by name, ignoring the fact that some of
them (tRFC and tREFI) need to be first accessed using the chosen refresh
mode.

This commit fixes this error, by properly using `key` parameter when
calling `SDRAMModule.get` method to get only required timing.

If one were to fix it in `DFITimingsChecker.prepare_timings` method,
it would require duplicating logic from `SDRAMModule.get` so this is a
simpler and cleaner solution.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2022-11-14 21:36:17 +01:00
Florent Kermarrec c770dd62ed test/test_lpddr5: Add tINIT2 as allowed warning. 2022-10-25 08:58:20 +02:00
Florent Kermarrec d1529d7508 ci: Bump to ubuntu 20.04. 2022-10-14 18:17:02 +02:00
Florent Kermarrec ae0763e252 axi: Update frontend/test with LiteX changes. 2022-09-15 17:52:01 +02:00
Florent Kermarrec 559dd24c99 phy/gw2ddrphy: Minor cosmetic cleanups. 2022-09-08 16:09:38 +02:00
Florent Kermarrec cff8500f52 phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS. 2022-09-08 16:03:39 +02:00
Florent Kermarrec 5b72d1a34a gw2ddrphy: Add TCLK_SOURCE on DQS's OSER4_MEM. 2022-09-08 10:49:54 +02:00
Florent Kermarrec ab9aec9129 phy/gw2ddrphy: Make oen signal names consistent. 2022-09-07 17:02:56 +02:00
Florent Kermarrec 22b823fdbc phy/gw2ddrphy: Use same BitSlip moduel than ECP5DDRPHY. 2022-09-07 16:58:15 +02:00
Florent Kermarrec f869d8e3d6 phy/gw2ddrphy: Increase similarities with ecp5ddrphy and add checkme notes. 2022-09-07 16:03:20 +02:00
Florent Kermarrec 434b00e65a phy/gw2ddrphy: Fix Vendor name, update copyright. 2022-09-07 12:14:11 +02:00
Icenowy Zheng c7eba6f704 Add intitial GW2DDRPHY (ported from ECP5DDRPHY), WIP. 2022-09-07 11:25:30 +02:00
Florent Kermarrec dfc03a26b3 CONTRIBUTORS: Update. 2022-09-07 10:18:59 +02:00
Florent Kermarrec 3d066c87f9 ci: Add comment for Verilator build/install. 2022-06-27 17:46:37 +02:00
Florent Kermarrec e662fadf8a test/test_init: Update. 2022-05-10 10:38:55 +02:00
Florent Kermarrec 85e4c995d8 litedram/gen: .init renaming no longer required with https://github.com/enjoy-digital/litex/pull/1293. 2022-05-09 18:02:57 +02:00
Florent Kermarrec 2b8af870c5 phy/usddrphy/Clk: Connect cdly_value only on first clk pad. 2022-05-02 17:34:52 +02:00
Florent Kermarrec 692355d120 CONTRIBUTORS: Update. 2022-05-02 13:43:38 +02:00
Florent Kermarrec 745f2a060a bench/targets: Use full imports. 2022-05-02 13:07:29 +02:00
Florent Kermarrec 47ddb03ec8 phy/rpc/arty: Use new I2C init to automatically inialize Vbucks and integrate modified DDR3 IOs (SSTL15). 2022-04-29 14:16:47 +02:00
Florent Kermarrec b313fe5224 phy/rpc/arty: Remove calls to add_csrs (No longer required) and fix build. 2022-04-29 13:13:38 +02:00
Florent Kermarrec 9e0d5ca22d phy/rpc: Add Arty target file that has used to validate RPC-DRAM. 2022-04-29 13:10:22 +02:00