351 lines
13 KiB
Python
Executable File
351 lines
13 KiB
Python
Executable File
#!/usr/bin/env python3
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import os
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import sys
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import math
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import struct
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.soc.cores.clock import *
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from litedram.core.controller import ControllerSettings
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.uart import *
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from litedram.frontend.axi import *
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from litedram.frontend.bist import LiteDRAMBISTGenerator
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from litedram.frontend.bist import LiteDRAMBISTChecker
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def get_common_ios():
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return [
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# clk / rst
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("clk", 0, Pins("X")),
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("rst", 0, Pins("X")),
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# serial
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("serial", 0,
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Subsignal("tx", Pins("X")),
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Subsignal("rx", Pins("X"))
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),
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# crg status
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("pll_locked", 0, Pins("X")),
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# init status
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("init_done", 0, Pins("X")),
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("init_error", 0, Pins("X")),
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# iodelay clk / rst
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("clk_iodelay", 0, Pins("X")),
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("rst_iodelay", 0, Pins("X")),
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# user clk / rst
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("user_clk", 0, Pins("X")),
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("user_rst", 0, Pins("X"))
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]
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def get_dram_ios(core_config):
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sdram_module = core_config["sdram_module"]
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return [
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("ddram", 0,
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Subsignal("a", Pins(
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"X "*log2_int(core_config["sdram_module"].nrows))),
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Subsignal("ba", Pins(
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"X "*log2_int(core_config["sdram_module"].nbanks))),
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Subsignal("ras_n", Pins("X")),
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Subsignal("cas_n", Pins("X")),
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Subsignal("we_n", Pins("X")),
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Subsignal("cs_n", Pins(
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"X "*core_config["sdram_rank_nb"])),
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Subsignal("dm", Pins(
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"X "*2*core_config["sdram_module_nb"])),
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Subsignal("dq", Pins(
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"X "*16*core_config["sdram_module_nb"])),
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Subsignal("dqs_p", Pins(
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"X "*2*core_config["sdram_module_nb"])),
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Subsignal("dqs_n", Pins(
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"X "*2*core_config["sdram_module_nb"])),
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Subsignal("clk_p", Pins(
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"X "*core_config["sdram_rank_nb"])),
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Subsignal("clk_n", Pins(
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"X "*core_config["sdram_rank_nb"])),
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Subsignal("cke", Pins(
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"X "*core_config["sdram_rank_nb"])),
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Subsignal("odt", Pins(
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"X "*core_config["sdram_rank_nb"])),
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Subsignal("reset_n", Pins("X"))
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),
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]
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def get_native_user_port_ios(_id, aw, dw):
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return [
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("user_port", _id,
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# cmd
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Subsignal("cmd_valid", Pins(1)),
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Subsignal("cmd_ready", Pins(1)),
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Subsignal("cmd_we", Pins(1)),
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Subsignal("cmd_addr", Pins(aw)),
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# wdata
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Subsignal("wdata_valid", Pins(1)),
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Subsignal("wdata_ready", Pins(1)),
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Subsignal("wdata_we", Pins(dw//8)),
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Subsignal("wdata_data", Pins(dw)),
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# rdata
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Subsignal("rdata_valid", Pins(1)),
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Subsignal("rdata_ready", Pins(1)),
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Subsignal("rdata_data", Pins(dw))
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),
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]
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def get_axi_user_port_ios(_id, aw, dw, iw):
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return [
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("user_port", _id,
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# aw
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Subsignal("aw_valid", Pins(1)),
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Subsignal("aw_ready", Pins(1)),
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Subsignal("aw_addr", Pins(aw)),
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Subsignal("aw_burst", Pins(2)),
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Subsignal("aw_len", Pins(8)),
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Subsignal("aw_size", Pins(4)),
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Subsignal("aw_id", Pins(iw)),
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# w
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Subsignal("w_valid", Pins(1)),
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Subsignal("w_ready", Pins(1)),
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Subsignal("w_last", Pins(1)),
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Subsignal("w_strb", Pins(dw//8)),
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Subsignal("w_data", Pins(dw)),
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# b
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Subsignal("b_valid", Pins(1)),
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Subsignal("b_ready", Pins(1)),
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Subsignal("b_resp", Pins(2)),
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Subsignal("b_id", Pins(iw)),
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# ar
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Subsignal("ar_valid", Pins(1)),
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Subsignal("ar_ready", Pins(1)),
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Subsignal("ar_addr", Pins(aw)),
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Subsignal("ar_burst", Pins(2)),
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Subsignal("ar_len", Pins(8)),
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Subsignal("ar_size", Pins(4)),
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Subsignal("ar_id", Pins(iw)),
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# r
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Subsignal("r_valid", Pins(1)),
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Subsignal("r_ready", Pins(1)),
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Subsignal("r_last", Pins(1)),
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Subsignal("r_resp", Pins(2)),
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Subsignal("r_data", Pins(dw)),
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Subsignal("r_id", Pins(iw))
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),
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]
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "", io=[], toolchain="vivado")
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class LiteDRAMCRG(Module):
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def __init__(self, platform, core_config):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_iodelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(platform.request("rst"))
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pll.register_clkin(platform.request("clk"), core_config["input_clk_freq"])
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pll.create_clkout(self.cd_sys, core_config["sys_clk_freq"])
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pll.create_clkout(self.cd_sys4x, 4*core_config["sys_clk_freq"])
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pll.create_clkout(self.cd_sys4x_dqs, 4*core_config["sys_clk_freq"], phase=90)
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pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay)
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self.comb += platform.request("pll_locked").eq(pll.locked)
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class LiteDRAMCoreControl(Module, AutoCSR):
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def __init__(self):
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self.init_done = CSRStorage()
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self.init_error = CSRStorage()
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class LiteDRAMCore(SoCSDRAM):
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csr_map = {
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"ddrctrl": 16,
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"ddrphy": 17
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}
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, platform, core_config, **kwargs):
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platform.add_extension(get_common_ios())
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sys_clk_freq = core_config["sys_clk_freq"]
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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cpu_type=core_config["cpu"],
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l2_size=32*core_config["sdram_module_nb"],
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reserve_nmi_interrupt=False,
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csr_data_width=8 if core_config["cpu"] is not None else 32,
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with_uart=core_config["cpu"] is not None,
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with_timer=core_config["cpu"] is not None,
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csr_expose=True,
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**kwargs)
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# crg
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self.submodules.crg = LiteDRAMCRG(platform, core_config)
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# sdram
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platform.add_extension(get_dram_ios(core_config))
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self.submodules.ddrphy = core_config["sdram_phy"](platform.request("ddram"), sys_clk_freq=sys_clk_freq,
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iodelay_clk_freq=core_config["iodelay_clk_freq"])
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self.ddrphy.settings.add_electrical_settings(
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rtt_nom=core_config["rtt_nom"],
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rtt_wr=core_config["rtt_wr"],
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ron=core_config["ron"])
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4", speedgrade=core_config["sdram_module_speedgrade"])
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controller_settings = controller_settings=ControllerSettings(
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cmd_buffer_depth=core_config["cmd_buffer_depth"],
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read_time=core_config["read_time"],
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write_time=core_config["write_time"])
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings,
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controller_settings=controller_settings)
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# sdram init
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self.submodules.ddrctrl = LiteDRAMCoreControl()
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self.add_constant("DDRPHY_HIGH_SKEW_DISABLE", None)
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self.comb += [
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platform.request("init_done").eq(self.ddrctrl.init_done.storage),
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platform.request("init_error").eq(self.ddrctrl.init_error.storage)
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]
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# user port
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self.comb += [
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platform.request("user_clk").eq(ClockSignal()),
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platform.request("user_rst").eq(ResetSignal())
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]
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if core_config["user_ports_type"] == "native":
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for i in range(core_config["user_ports_nb"]):
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user_port = self.sdram.crossbar.get_port()
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platform.add_extension(get_native_user_port_ios(i,
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user_port.address_width,
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user_port.data_width))
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_user_port_io = platform.request("user_port", i)
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self.comb += [
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# cmd
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user_port.cmd.valid.eq(_user_port_io.cmd_valid),
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_user_port_io.cmd_ready.eq(user_port.cmd.ready),
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user_port.cmd.we.eq(_user_port_io.cmd_we),
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user_port.cmd.addr.eq(_user_port_io.cmd_addr),
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# wdata
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user_port.wdata.valid.eq(_user_port_io.wdata_valid),
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_user_port_io.wdata_ready.eq(user_port.wdata.ready),
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user_port.wdata.we.eq(_user_port_io.wdata_we),
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user_port.wdata.data.eq(_user_port_io.wdata_data),
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# rdata
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_user_port_io.rdata_valid.eq(user_port.rdata.valid),
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user_port.rdata.ready.eq(_user_port_io.rdata_ready),
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_user_port_io.rdata_data.eq(user_port.rdata.data),
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]
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elif core_config["user_ports_type"] == "axi":
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for i in range(core_config["user_ports_nb"]):
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user_port = self.sdram.crossbar.get_port()
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axi_port = LiteDRAMAXIPort(
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user_port.data_width,
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user_port.address_width + log2_int(user_port.data_width//8),
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core_config["user_ports_id_width"])
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axi2native = LiteDRAMAXI2Native(axi_port, user_port)
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self.submodules += axi2native
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platform.add_extension(get_axi_user_port_ios(i,
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axi_port.address_width,
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axi_port.data_width,
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core_config["user_ports_id_width"]))
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_axi_port_io = platform.request("user_port", i)
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self.comb += [
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# aw
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axi_port.aw.valid.eq(_axi_port_io.aw_valid),
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_axi_port_io.aw_ready.eq(axi_port.aw.ready),
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axi_port.aw.addr.eq(_axi_port_io.aw_addr),
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axi_port.aw.burst.eq(_axi_port_io.aw_burst),
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axi_port.aw.len.eq(_axi_port_io.aw_len),
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axi_port.aw.size.eq(_axi_port_io.aw_size),
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axi_port.aw.id.eq(_axi_port_io.aw_id),
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# w
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axi_port.w.valid.eq(_axi_port_io.w_valid),
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_axi_port_io.w_ready.eq(axi_port.w.ready),
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axi_port.w.last.eq(_axi_port_io.w_last),
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axi_port.w.strb.eq(_axi_port_io.w_strb),
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axi_port.w.data.eq(_axi_port_io.w_data),
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# b
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_axi_port_io.b_valid.eq(axi_port.b.valid),
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axi_port.b.ready.eq(_axi_port_io.b_ready),
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_axi_port_io.b_resp.eq(axi_port.b.resp),
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_axi_port_io.b_id.eq(axi_port.b.id),
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# ar
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axi_port.ar.valid.eq(_axi_port_io.ar_valid),
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_axi_port_io.ar_ready.eq(axi_port.ar.ready),
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axi_port.ar.addr.eq(_axi_port_io.ar_addr),
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axi_port.ar.burst.eq(_axi_port_io.ar_burst),
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axi_port.ar.len.eq(_axi_port_io.ar_len),
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axi_port.ar.size.eq(_axi_port_io.ar_size),
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axi_port.ar.id.eq(_axi_port_io.ar_id),
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# r
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_axi_port_io.r_valid.eq(axi_port.r.valid),
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axi_port.r.ready.eq(_axi_port_io.r_ready),
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_axi_port_io.r_last.eq(axi_port.r.last),
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_axi_port_io.r_resp.eq(axi_port.r.resp),
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_axi_port_io.r_data.eq(axi_port.r.data),
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_axi_port_io.r_id.eq(axi_port.r.id),
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]
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else:
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raise ValueError("Unsupported port type: {}".format(core_config["user_ports_type"]))
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def main():
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# get config
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if len(sys.argv) < 2:
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print("missing config file")
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exit(1)
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exec(open(sys.argv[1]).read(), globals())
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# generate core
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platform = Platform()
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soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
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builder = Builder(soc, output_dir="build", compile_gateware=False)
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vns = builder.build(build_name="litedram_core", regular_comb=False)
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# prepare core (could be improved)
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def replace_in_file(filename, _from, _to):
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# Read in the file
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with open(filename, "r") as file :
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filedata = file.read()
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# Replace the target string
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filedata = filedata.replace(_from, _to)
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# Write the file out again
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with open(filename, 'w') as file:
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file.write(filedata)
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init_filename = "mem.init"
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os.system("mv build/gateware/{} build/gateware/litedram_core.init".format(init_filename))
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replace_in_file("build/gateware/litedram_core.v", init_filename, "litedram_core.init")
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if __name__ == "__main__":
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main()
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