litedram/litedram
055cbdbc43 tRRD is specified incorrectly. 2018-10-11 16:57:24 -04:00
..
core Fix issue where we ignore important timing parameters. 2018-10-11 16:56:36 -04:00
frontend Revert "Further timing improvements" + Bug fixes 2018-10-04 00:03:12 -04:00
phy s6ddrphy: Pass missing nranks parameter. 2018-09-18 16:58:07 -07:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py Use tXXDController everywhere (better timing). Also fix a bug in the previous commit for cmd.is_activate 2018-10-02 22:48:36 -04:00
dfii.py multirank: one cs_n/cke/odt/clk per rank 2018-09-09 14:32:15 +02:00
modules.py tRRD is specified incorrectly. 2018-10-11 16:57:24 -04:00
sdram_init.py sdram_init: min value for wr is 5 2018-09-05 23:40:04 +02:00