246 lines
8.0 KiB
Python
246 lines
8.0 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import random
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import unittest
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import itertools
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import collections
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from migen import *
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from litex.soc.interconnect import stream
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from litedram.common import *
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from litedram.core.bandwidth import Bandwidth
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from test.common import timeout_generator, CmdRequestRWDriver
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class BandwidthDUT(Module):
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def __init__(self, data_width=8, **kwargs):
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a, ba = 13, 3
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self.cmd = stream.Endpoint(cmd_request_rw_layout(a, ba))
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self.submodules.bandwidth = Bandwidth(self.cmd, data_width, **kwargs)
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class CommandDriver:
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def __init__(self, cmd, cmd_options=None):
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self.cmd = cmd
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self.driver = CmdRequestRWDriver(cmd)
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self.cmd_counts = collections.defaultdict(int)
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@passive
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def random_generator(self, random_ready_max=20, commands=None):
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commands = commands or ["read", "write"]
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prng = random.Random(42)
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while True:
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# Generate random command
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command = prng.choice(commands)
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yield from getattr(self.driver, command)()
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yield
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# Wait some times before it becomes ready
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for _ in range(prng.randint(0, random_ready_max)):
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yield
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yield self.cmd.ready.eq(1)
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yield
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self.cmd_counts[command] += 1
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yield self.cmd.ready.eq(0)
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# Disable command
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yield from self.driver.nop()
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yield
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@passive
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def timeline_generator(self, timeline):
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# Timeline: an iterator of tuples (cycle, command)
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sim_cycle = 0
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for cycle, command in timeline:
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assert cycle >= sim_cycle
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while sim_cycle != cycle:
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sim_cycle += 1
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yield
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# Set the command
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yield from getattr(self.driver, command)()
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yield self.cmd.ready.eq(1)
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self.cmd_counts[command] += 1
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# Advance 1 cycle
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yield
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sim_cycle += 1
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# Clear state
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yield self.cmd.ready.eq(0)
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yield from self.driver.nop()
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class TestBandwidth(unittest.TestCase):
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def test_can_read_status_data_width(self):
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# Verify that data width can be read from a CSR.
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def test(data_width):
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def main_generator(dut):
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yield
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self.assertEqual((yield dut.bandwidth.data_width.status), data_width)
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dut = BandwidthDUT(data_width=data_width)
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run_simulation(dut, main_generator(dut))
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for data_width in [8, 16, 32, 64]:
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with self.subTest(data_width=data_width):
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test(data_width)
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def test_requires_update_to_copy_the_data(self):
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# Verify that command counts are copied to CSRs only after `update`.
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def main_generator(dut):
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nreads = (yield from dut.bandwidth.nreads.read())
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nwrites = (yield from dut.bandwidth.nwrites.read())
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self.assertEqual(nreads, 0)
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self.assertEqual(nwrites, 0)
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# Wait enough for the period to end
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for _ in range(2**6):
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yield
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nreads = (yield from dut.bandwidth.nreads.read())
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nwrites = (yield from dut.bandwidth.nwrites.read())
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self.assertEqual(nreads, 0)
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self.assertEqual(nwrites, 0)
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# Update register values
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yield from dut.bandwidth.update.write(1)
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nreads = (yield from dut.bandwidth.nreads.read())
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nwrites = (yield from dut.bandwidth.nwrites.read())
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self.assertNotEqual((nreads, nwrites), (0, 0))
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dut = BandwidthDUT(period_bits=6)
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cmd_driver = CommandDriver(dut.cmd)
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generators = [
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main_generator(dut),
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cmd_driver.random_generator(),
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]
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run_simulation(dut, generators)
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def test_correct_read_write_counts(self):
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# Verify that the number of registered READ/WRITE commands is correct.
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results = {}
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def main_generator(dut):
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# Wait for the first period to end
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for _ in range(2**8):
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yield
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yield from dut.bandwidth.update.write(1)
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yield
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results["nreads"] = (yield from dut.bandwidth.nreads.read())
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results["nwrites"] = (yield from dut.bandwidth.nwrites.read())
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dut = BandwidthDUT(period_bits=8)
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cmd_driver = CommandDriver(dut.cmd)
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generators = [
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main_generator(dut),
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cmd_driver.random_generator(),
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]
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run_simulation(dut, generators)
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self.assertEqual(results["nreads"], cmd_driver.cmd_counts["read"])
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def test_counts_read_write_only(self):
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# Verify that only READ and WRITE commands are registered.
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results = {}
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def main_generator(dut):
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# Wait for the first period to end
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for _ in range(2**8):
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yield
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yield from dut.bandwidth.update.write(1)
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yield
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results["nreads"] = (yield from dut.bandwidth.nreads.read())
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results["nwrites"] = (yield from dut.bandwidth.nwrites.read())
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dut = BandwidthDUT(period_bits=8)
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cmd_driver = CommandDriver(dut.cmd)
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commands = ["read", "write", "activate", "precharge", "refresh"]
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generators = [
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main_generator(dut),
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cmd_driver.random_generator(commands=commands),
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]
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run_simulation(dut, generators)
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self.assertEqual(results["nreads"], cmd_driver.cmd_counts["read"])
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def test_correct_period_length(self):
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# Verify that period length is correct by measuring time between CSR changes.
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period_bits = 5
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period = 2**period_bits
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n_per_period = {0: 3, 1: 6, 2: 9}
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timeline = {}
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for p, n in n_per_period.items():
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for i in range(n):
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margin = 10
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timeline[period*p + margin + i] = "write"
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def main_generator(dut):
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# Keep the values always up to date
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yield dut.bandwidth.update.re.eq(1)
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# Wait until we have the data from 1st period
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while (yield dut.bandwidth.nwrites.status) != 3:
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yield
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# Count time to next period
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cycles = 0
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while (yield dut.bandwidth.nwrites.status) != 6:
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cycles += 1
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yield
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self.assertEqual(cycles, period)
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dut = BandwidthDUT(period_bits=period_bits)
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cmd_driver = CommandDriver(dut.cmd)
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generators = [
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main_generator(dut),
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cmd_driver.timeline_generator(timeline.items()),
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timeout_generator(period * 3),
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]
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run_simulation(dut, generators)
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def test_not_missing_commands_on_period_boundary(self):
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# Verify that no data is lost in the cycle when new period starts.
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period_bits = 5
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period = 2**period_bits
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# Start 10 cycles before period ends, end 10 cycles after it ends
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base = period - 10
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nwrites = 20
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timeline = {base + i: "write" for i in range(nwrites)}
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def main_generator(dut):
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# Wait until 1st period ends (+ some margin)
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for _ in range(period + 10):
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yield
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# Read the count from 1st period
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yield from dut.bandwidth.update.write(1)
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yield
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nwrites_registered = (yield from dut.bandwidth.nwrites.read())
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# Wait until 2nd period ends
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for _ in range(period):
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yield
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# Read the count from 1st period
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yield from dut.bandwidth.update.write(1)
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yield
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nwrites_registered += (yield from dut.bandwidth.nwrites.read())
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self.assertEqual(nwrites_registered, nwrites)
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dut = BandwidthDUT(period_bits=period_bits)
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cmd_driver = CommandDriver(dut.cmd)
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generators = [
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main_generator(dut),
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cmd_driver.timeline_generator(timeline.items()),
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]
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run_simulation(dut, generators)
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