117 lines
4.3 KiB
Markdown
117 lines
4.3 KiB
Markdown
```
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__ _ __ ___ ___ ___ __ ___
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/ / (_) /____ / _ \/ _ \/ _ | / |/ /
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/ /__/ / __/ -_) // / , _/ __ |/ /|_/ /
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/____/_/\__/\__/____/_/|_/_/ |_/_/ /_/
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Copyright 2015-2022 / EnjoyDigital
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A small footprint and configurable DRAM core
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powered by Migen & LiteX
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```
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[](https://github.com/enjoy-digital/litedram/actions) 
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[> Intro
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--------
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LiteDRAM provides a small footprint and configurable DRAM core.
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LiteDRAM is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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Using Migen to describe the HDL allows the core to be highly and easily configurable.
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LiteDRAM can be used as LiteX library or can be integrated with your standard
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design flow by generating the verilog rtl that you will use as a standard core.
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[> Features
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-----------
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PHY:
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- Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
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- Xilinx Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
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- Xilinx Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
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- Xilinx Kintex/Virtex Ultrascale (Plus) DDR3/DDR4 PHY (1:4 frequency ratio)
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- Lattice ECP5 DDR3 PHY (1:2 frequency ratio)
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- Gowin G2A DDR3 PHY (1:2 frequency ratio)
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Core:
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- Fully pipelined, high performance.
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- Configurable commands depth on bankmachines.
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- Auto-Precharge.
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- Periodic refresh/ZQ short calibration (up to 8 postponed refreshes).
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Frontend:
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- Configurable crossbar (simply use crossbar.get_port() to add a new port!)
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- Ports arbitration transparent to the user.
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- Native, AXI-MM or Wishbone user interface.
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- DMA reader/writer.
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- BIST.
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- ECC (Error-correcting code)
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[> FPGA Proven
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---------------
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LiteDRAM is already used in commercial and open-source designs:
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- HDMI2USB: http://hdmi2usb.tv/home/
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- NeTV2: https://www.crowdsupply.com/alphamax/netv2
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- USBSniffer: http://blog.lambdaconcept.com/doku.php?id=products:usb_sniffer
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- and others commercial designs...
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[> Possible improvements
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------------------------
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- add Avalon-ST interface.
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- add support for Altera devices.
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- add more documentation
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr.
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[> Getting started
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------------------
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1. Install Python 3.6+ and FPGA vendor's development tools.
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2. Install LiteX and the cores by following the LiteX's wiki [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation).
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3. You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.
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[> Tests
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--------
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Unit tests are available in ./test/.
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To run all the unit tests:
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```sh
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$ ./setup.py test
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```
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Tests can also be run individually:
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```sh
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$ python3 -m unittest test.test_name
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```
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[> License
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----------
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LiteDRAM is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteDRAM for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteDRAM
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- cite LiteDRAM in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteDRAM.
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[> Support and consulting
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-------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteDRAM is developed and maintained by EnjoyDigital.
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If you would like to know more about LiteDRAM or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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----------
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E-mail: florent [AT] enjoy-digital.fr |