154 lines
6.5 KiB
Python
Executable File
154 lines
6.5 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
#
|
|
# This file is part of LiteDRAM.
|
|
#
|
|
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
import os
|
|
import argparse
|
|
|
|
from migen import *
|
|
|
|
from litex_boards.platforms import digilent_genesys2
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.interconnect.csr import *
|
|
from litex.soc.integration.soc_core import *
|
|
from litex.soc.integration.builder import *
|
|
|
|
from litedram.phy import s7ddrphy
|
|
from litedram.modules import MT41J256M16
|
|
|
|
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(Module, AutoCSR):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.rst = Signal()
|
|
self.clock_domains.cd_sys_pll = ClockDomain()
|
|
self.clock_domains.cd_sys = ClockDomain()
|
|
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
|
|
self.clock_domains.cd_clk200 = ClockDomain()
|
|
self.clock_domains.cd_uart = ClockDomain()
|
|
|
|
# # #
|
|
|
|
# Main PLL.
|
|
self.submodules.main_pll = main_pll = S7PLL(speedgrade=-2)
|
|
self.comb += main_pll.reset.eq(~platform.request("cpu_reset_n"))
|
|
main_pll.register_clkin(platform.request("clk200"), 200e6)
|
|
main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
|
|
main_pll.create_clkout(self.cd_clk200, 200e6)
|
|
main_pll.create_clkout(self.cd_uart, 100e6)
|
|
main_pll.expose_drp()
|
|
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
|
|
|
|
# DRAM PLL.
|
|
self.submodules.pll = pll = S7PLL(speedgrade=-2)
|
|
self.comb += pll.reset.eq(~main_pll.locked | self.rst)
|
|
pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
|
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
|
|
|
|
# Sys Clk Counter.
|
|
self.sys_clk_counter = CSRStatus(32)
|
|
self.sync += self.sys_clk_counter.status.eq(self.sys_clk_counter.status + 1)
|
|
|
|
# Bench SoC ----------------------------------------------------------------------------------------
|
|
|
|
class BenchSoC(SoCCore):
|
|
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
|
|
platform = digilent_genesys2.Platform()
|
|
|
|
# SoCCore ----------------------------------------------------------------------------------
|
|
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
|
|
ident = "LiteDRAM bench on Genesys2",
|
|
integrated_rom_size = 0x10000,
|
|
integrated_rom_mode = "rw",
|
|
uart_name = uart)
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
|
|
|
# DDR3 SDRAM -------------------------------------------------------------------------------
|
|
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
|
|
memtype = "DDR3",
|
|
nphases = 4,
|
|
sys_clk_freq = sys_clk_freq)
|
|
self.add_sdram("sdram",
|
|
phy = self.ddrphy,
|
|
module = MT41J256M16(sys_clk_freq, "1:4"),
|
|
origin = self.mem_map["main_ram"],
|
|
with_bist = with_bist)
|
|
|
|
# UARTBone ---------------------------------------------------------------------------------
|
|
if uart != "serial":
|
|
self.add_uartbone(clk_freq=100e6, baudrate=115200, cd="uart")
|
|
|
|
# Etherbone --------------------------------------------------------------------------------
|
|
self.submodules.ethphy = LiteEthPHYRGMII(
|
|
clock_pads = self.platform.request("eth_clocks"),
|
|
pads = self.platform.request("eth"),
|
|
with_hw_init_reset = False)
|
|
self.add_etherbone(phy=self.ethphy)
|
|
|
|
# Analyzer ---------------------------------------------------------------------------------
|
|
if with_analyzer:
|
|
from litescope import LiteScopeAnalyzer
|
|
analyzer_signals = [self.ddrphy.dfi]
|
|
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
|
|
depth = 512,
|
|
clock_domain = "sys",
|
|
csr_csv = "analyzer.csv")
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
|
from litex.soc.cores.led import LedChaser
|
|
self.submodules.leds = LedChaser(
|
|
pads = platform.request_all("user_led"),
|
|
sys_clk_freq = sys_clk_freq)
|
|
|
|
# Main ---------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(description="LiteDRAM Bench on Genesys2")
|
|
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
|
|
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
|
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
|
|
parser.add_argument("--with-analyzer", action="store_true", help="Add Analyzer")
|
|
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
|
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
|
|
parser.add_argument("--sys-clk-freq", default=None, help="Set sys_clk_freq")
|
|
parser.add_argument("--test", action="store_true", help="Run Full Bench")
|
|
args = parser.parse_args()
|
|
|
|
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
|
|
builder = Builder(soc, output_dir="build/digilent_genesys2", csr_csv="csr.csv")
|
|
builder.build(run=args.build)
|
|
|
|
if args.load:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
|
|
|
if args.load_bios:
|
|
from common import load_bios
|
|
load_bios("build/digilent_genesys2/software/bios/bios.bin")
|
|
|
|
if args.sys_clk_freq is not None:
|
|
from common import s7_set_sys_clk
|
|
s7_set_sys_clk(clk_freq=float(args.sys_clk_freq), vco_freq=soc.crg.main_pll.compute_config()["vco"])
|
|
|
|
if args.test:
|
|
from common import s7_bench_test
|
|
s7_bench_test(
|
|
freq_min = 60e6,
|
|
freq_max = 180e6,
|
|
freq_step = 1e6,
|
|
vco_freq = soc.crg.main_pll.compute_config()["vco"],
|
|
bios_filename = "build/digilent_genesys2/software/bios/bios.bin")
|
|
|
|
if __name__ == "__main__":
|
|
main()
|