327 lines
12 KiB
Python
327 lines
12 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import random
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from migen import *
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from litedram.common import *
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from litedram.frontend.ecc import *
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from litex.gen.sim import *
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from litex.soc.cores.ecc import *
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from test.common import *
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# Helpers ------------------------------------------------------------------------------------------
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def bits(value, width=32):
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# Convert int to a string representing binary value and reverse it so that we can index bits
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# easily with s[0] being LSB
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return f"{value:0{width}b}"[::-1]
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def frombits(bits):
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# Reverse of bits()
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return int(bits[::-1], 2)
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def bits_pp(value, width=32):
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# Pretty print binary value, groupped by bytes
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if isinstance(value, str):
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value = frombits(value)
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s = f"{value:0{width}b}"
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byte_chunks = [s[i:i+8] for i in range(0, len(s), 8)]
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return "0b " + " ".join(byte_chunks)
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def extract_ecc_data(data_width, codeword_width, codeword_bits):
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extracted = ""
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for i in range(8):
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word = codeword_bits[codeword_width*i:codeword_width*(i+1)]
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# Remove parity bit
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word = word[1:]
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data_pos = compute_data_positions(codeword_width - 1) # -1 for parity
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# Extract data bits
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word_ex = list(bits(0, 32))
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for j, d in enumerate(data_pos):
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word_ex[j] = word[d-1]
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word_ex = "".join(word_ex)
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extracted += word_ex
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return extracted
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# TestECC ------------------------------------------------------------------------------------------
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class TestECC(unittest.TestCase):
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def test_eccw_connected(self):
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# Verify LiteDRAMNativePortECCW ECC encoding.
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class DUT(Module):
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def __init__(self):
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eccw = LiteDRAMNativePortECCW(data_width_from=32*8, data_width_to=39*8)
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self.submodules.eccw = eccw
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def main_generator(dut):
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sink_data = seed_to_data(0, nbits=32*8)
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yield dut.eccw.sink.data.eq(sink_data)
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yield
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source_data = (yield dut.eccw.source.data)
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sink_data_bits = bits(sink_data, 32*8)
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source_data_bits = bits(source_data, 39*8)
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self.assertNotEqual(sink_data_bits, source_data_bits[:len(sink_data_bits)])
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source_extracted = extract_ecc_data(32, 39, source_data_bits)
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# Assert each word separately for more readable assert messages
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for i in range(8):
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word = slice(32*i, 32*(i+1))
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self.assertEqual(bits_pp(source_extracted[word]), bits_pp(sink_data_bits[word]),
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msg=f"Mismatch at i = {i}")
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dut = DUT()
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run_simulation(dut, main_generator(dut))
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def test_eccw_we_enabled(self):
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# Verify LiteDRAMNativePortECCW always set bytes enable.
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class DUT(Module):
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def __init__(self):
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eccw = LiteDRAMNativePortECCW(data_width_from=32*8, data_width_to=39*8)
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self.submodules.eccw = eccw
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self.comb += eccw.sink.we.eq(2**(32*8)-1)
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def main_generator(dut):
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yield
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source_we = (yield dut.eccw.source.we)
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self.assertEqual(bits_pp(source_we, 39//8), bits_pp(2**len(dut.eccw.source.we) - 1))
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dut = DUT()
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run_simulation(dut, main_generator(dut))
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def test_eccr_connected(self):
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# Verify LiteDRAMNativePortECCR ECC decoding.
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class DUT(Module):
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def __init__(self):
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eccr = LiteDRAMNativePortECCR(data_width_from=32*8, data_width_to=39*8)
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self.submodules.eccr = eccr
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def main_generator(dut):
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sink_data = seed_to_data(0, nbits=(39*8 // 32 + 1) * 32)
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yield dut.eccr.sink.data.eq(sink_data)
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yield
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source_data = (yield dut.eccr.source.data)
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sink_data_bits = bits(sink_data, 39*8)
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source_data_bits = bits(source_data, 32*8)
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self.assertNotEqual(sink_data_bits[:len(source_data_bits)], source_data_bits)
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sink_extracted = extract_ecc_data(32, 39, sink_data_bits)
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self.assertEqual(bits_pp(sink_extracted), bits_pp(source_data_bits))
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# Assert each word separately for more readable assert messages
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for i in range(8):
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word = slice(32*i, 32*(i+1))
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self.assertEqual(bits_pp(sink_extracted[word]), bits_pp(source_data_bits[word]),
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msg=f"Mismatch at i = {i}")
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dut = DUT()
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run_simulation(dut, main_generator(dut))
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def test_eccr_errors_connected_when_sink_valid(self):
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# Verify LiteDRAMNativePortECCR Error detection.
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class DUT(Module):
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def __init__(self):
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eccr = LiteDRAMNativePortECCR(data_width_from=32*8, data_width_to=39*8)
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self.submodules.eccr = eccr
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def main_generator(dut):
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yield dut.eccr.enable.eq(1)
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yield dut.eccr.sink.data.eq(0b10) # Wrong parity bit
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yield
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# Verify no errors are detected
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self.assertEqual((yield dut.eccr.sec), 0)
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self.assertEqual((yield dut.eccr.ded), 0)
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# Set sink.valid and verify errors parity error is detected
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yield dut.eccr.sink.valid.eq(1)
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yield
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self.assertEqual((yield dut.eccr.sec), 1)
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self.assertEqual((yield dut.eccr.ded), 0)
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dut = DUT()
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run_simulation(dut, main_generator(dut))
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def ecc_encode_decode_test(self, from_width, to_width, n, pre=None, post=None, **kwargs):
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"""ECC encoding/decoding generic test."""
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class DUT(Module):
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def __init__(self):
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self.port_from = LiteDRAMNativePort("both", 24, from_width)
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self.port_to = LiteDRAMNativePort("both", 24, to_width)
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self.submodules.ecc = LiteDRAMNativePortECC(self.port_from, self.port_to, **kwargs)
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self.mem = DRAMMemory(to_width, n)
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self.wdata = [seed_to_data(i, nbits=from_width) for i in range(n)]
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self.rdata = []
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def main_generator(dut):
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if pre is not None:
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yield from pre(dut)
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port = dut.port_from
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# Write
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for i in range(n):
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yield port.cmd.valid.eq(1)
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yield port.cmd.we.eq(1)
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yield port.cmd.addr.eq(i)
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yield
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while (yield port.cmd.ready) == 0:
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yield
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yield port.cmd.valid.eq(0)
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yield
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yield port.wdata.valid.eq(1)
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yield port.wdata.we.eq(2**from_width-1)
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yield port.wdata.data.eq(dut.wdata[i])
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yield
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while (yield port.wdata.ready) == 0:
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yield
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yield port.wdata.valid.eq(0)
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yield
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# Read
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for i in range(n):
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yield port.cmd.valid.eq(1)
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yield port.cmd.we.eq(0)
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yield port.cmd.addr.eq(i)
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yield
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while (yield port.cmd.ready) == 0:
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yield
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yield port.cmd.valid.eq(0)
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yield
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while (yield port.rdata.valid) == 0:
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yield
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dut.rdata.append((yield port.rdata.data))
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yield port.rdata.ready.eq(1)
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yield
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yield port.rdata.ready.eq(0)
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yield
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if post is not None:
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yield from post(dut)
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dut = DUT()
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generators = [
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main_generator(dut),
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dut.mem.write_handler(dut.port_to),
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dut.mem.read_handler(dut.port_to),
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]
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run_simulation(dut, generators)
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return dut
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def test_ecc_32_7(self):
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# Verify encoding/decoding on 32 data bits + 6 code bits + parity bit.
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dut = self.ecc_encode_decode_test(32*8, 39*8, 2)
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self.assertEqual(dut.wdata, dut.rdata)
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def test_ecc_64_8(self):
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# Verify encoding/decoding on 64 data bits + 7 code bits + parity bit.
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dut = self.ecc_encode_decode_test(64*8, 72*8, 2)
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self.assertEqual(dut.wdata, dut.rdata)
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def test_ecc_sec_errors(self):
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# Verify SEC errors detection/correction with 1-bit flip.
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def pre(dut):
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yield from dut.ecc.flip.write(0b00000100)
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def post(dut):
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dut.sec_errors = (yield from dut.ecc.sec_errors.read())
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dut.ded_errors = (yield from dut.ecc.ded_errors.read())
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dut = self.ecc_encode_decode_test(8*8, 13*8, 4, pre, post, with_error_injection=True)
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self.assertEqual(dut.wdata, dut.rdata)
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self.assertEqual(dut.sec_errors, 4)
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self.assertEqual(dut.ded_errors, 0)
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def test_ecc_ded_errors(self):
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# Verify DED errors detection with 2-bit flip.
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def pre(dut):
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yield from dut.ecc.flip.write(0b00001100)
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def post(dut):
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dut.sec_errors = (yield from dut.ecc.sec_errors.read())
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dut.ded_errors = (yield from dut.ecc.ded_errors.read())
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dut = self.ecc_encode_decode_test(8*8, 13*8, 4, pre, post, with_error_injection=True)
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self.assertNotEqual(dut.wdata, dut.rdata)
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self.assertEqual(dut.sec_errors, 0)
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self.assertEqual(dut.ded_errors, 4)
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def test_ecc_decoder_disable(self):
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# Verify enable control.
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def pre(dut):
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yield from dut.ecc.flip.write(0b10101100)
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yield from dut.ecc.enable.write(0)
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def post(dut):
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dut.sec_errors = (yield from dut.ecc.sec_errors.read())
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dut.ded_errors = (yield from dut.ecc.ded_errors.read())
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dut = self.ecc_encode_decode_test(8*8, 13*8, 4, pre, post, with_error_injection=True)
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self.assertNotEqual(dut.wdata, dut.rdata)
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self.assertEqual(dut.sec_errors, 0)
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self.assertEqual(dut.ded_errors, 0)
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def test_ecc_clear_sec_errors(self):
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# Verify SEC errors clear.
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def pre(dut):
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yield from dut.ecc.flip.write(0b00000100)
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def post(dut):
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# Read errors after test (SEC errors expected)
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dut.sec_errors = (yield from dut.ecc.sec_errors.read())
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dut.ded_errors = (yield from dut.ecc.ded_errors.read())
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# Clear errors counters
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yield from dut.ecc.clear.write(1)
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yield
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# Re-Read errors to verify clear
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dut.sec_errors_c = (yield from dut.ecc.sec_errors.read())
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dut.ded_errors_c = (yield from dut.ecc.ded_errors.read())
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dut = self.ecc_encode_decode_test(8*8, 13*8, 4, pre, post, with_error_injection=True)
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self.assertEqual(dut.wdata, dut.rdata)
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self.assertNotEqual(dut.sec_errors, 0)
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self.assertEqual(dut.ded_errors, 0)
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self.assertEqual(dut.sec_errors_c, 0)
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self.assertEqual(dut.ded_errors_c, 0)
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def test_ecc_clear_ded_errors(self):
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# Verify DED errors clear.
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def pre(dut):
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yield from dut.ecc.flip.write(0b10101100)
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def post(dut):
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# Read errors after test (DED errors expected)
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dut.sec_errors = (yield from dut.ecc.sec_errors.read())
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dut.ded_errors = (yield from dut.ecc.ded_errors.read())
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# Clear errors counters
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yield from dut.ecc.clear.write(1)
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yield
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# Re-Read errors to verify clear
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dut.sec_errors_c = (yield from dut.ecc.sec_errors.read())
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dut.ded_errors_c = (yield from dut.ecc.ded_errors.read())
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dut = self.ecc_encode_decode_test(8*8, 13*8, 4, pre, post, with_error_injection=True)
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self.assertNotEqual(dut.wdata, dut.rdata)
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self.assertEqual(dut.sec_errors, 0)
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self.assertNotEqual(dut.ded_errors, 0)
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self.assertEqual(dut.sec_errors_c, 0)
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self.assertEqual(dut.ded_errors_c, 0)
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if __name__ == "__main__":
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unittest.main()
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